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as3606 as3607 system pmu with hv back light driver www.austriamicrosystems.com revision 1.03 1 - 70 data sheet 1 general description the as3606/07 is an ultra compact system pmu with integrated battery charger and hv back light driver. the device offers advanced power management functions. all necessary ics and peripherals in a battery powered mobile device are supplied by the as3606/07. it features 3 dcdc converters as well as 5 low noise ldos. the different regulated supply voltages are programmable via the serial control interface. the step-up converter for the backlight can operate up to 30v. both constant voltage (oled supply) as well as constant current (white led backlight) operations with 2 current sinks are possible. an internal voltage protection is limiting the output voltage in the case of external component failures. as3606/07 also contains a li-ion battery charger with constant current and constant voltage. the maximum charging current is 1a. an integrated battery switch and an optional external switch are separating the battery during charging or whenever an external power supply is present. with this switch it is also possible to operate with no or deeply discharged batteries. a programmable current limit can be used to control the maximum current used from a usb supply. the single supply voltage may vary from 2.7v to 5.5v. 2 key features power management voltage generation 3 dcdc step down regulators - dvm (0.61v-3.3v, 700ma) - 50a quiescent current - selectable switching frequency (2 or 1mhz) - 1.4a with combined dcdc 2 & 3 1 ldo low noise 2.7v (2.3-3.5v), 100ma 3 or 4 ldos low noise - 1.2-3.5v; 150/250ma - 30a quiescent current (low power mode) power supply supervision (ldo5) 4sec and 8sec emergency shut-down hibernation function hv backlight driver step up for 30v backlight with internal transistor voltage control mode and over-voltage protection 2 programmable current sink (max. 38ma) max. 20ma@50v (with ext. transistor) or 500ma@5v possible external pwm dimming input battery charger prog. trickle charging (25-265ma) prog. constant current charging (94-1060ma) prog. constant voltage charging (3.9v-4.25v) charger time-out and temperature supervision selectable current limitation for usb mode integrated battery switch & ideal diode external battery switch control output general battery and temperature supervisor 2 or 4 general purpose ios 10bit general purpose adc input pwm dimming input or wake-up input status output for: charger, low battery, power good and power- up key otp programmable boot sequence programmable regulator default voltages programmable start-up sequence applicable for ldo 1-4 and dcdc 1-3 control interface i2c control lines, including watchdog power-up input interrupt output bidirectional reset, with selectable delay low power standby mode, 160a with ldo5 on power-on reset circuit packaging qfn32 5x5mm or qfn36 6x6mm, 0.5mm pitch 3 application the devices are ideal for portable media players and portable navigation devices, e-books, tablet pcs, etc ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 2 - 70 as3606 as3607 2v2 data sheet - application figure 1. as3606 block diagram figure 2. as3607 block diagram ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 3 - 70 as3606 as3607 2v2 data sheet - contents contents 1 general description ......................................................................................................... ......................................................... 1 2 key features................................................................................................................ ............................................................. 1 3 application ................................................................................................................................................................................ 1 4 pin assignments ....................................................................................................................................................................... 5 4.1 pin descriptions.................................................................................................................................................................................... 6 5 absolute maximum ratings .................................................................................................... .................................................. 8 6 electrical characteristics.................................................................................................. ......................................................... 9 7 typical operating characteristics ........................................................................................... ................................................ 11 8 detailed description - power management functions........................................................................... ................................. 12 8.1 low drop out regulators ................................................................................................... ................................................................ 12 8.1.1 ldo5 .................................................................................................................... ..................................................................... 12 8.1.2 ldo 1, ldo2, ldo3 & ldo4.................................................................................................................................................... 13 8.1.3 parameter ............................................................................................................... ................................................................... 13 8.2 dcdc step-down converter.................................................................................................. ............................................................ 15 8.2.1 functional description ............................................................................................................................................................... 16 8.2.2 parameter ............................................................................................................... ................................................................... 17 8.3 30v step-up dcdc converter................................................................................................ ........................................................... 19 8.3.1 voltage feedback and ov protection ....................................................................................................................................... 19 8.3.2 voltage feedback........................................................................................................ .............................................................. 19 8.3.3 dls & dimming ........................................................................................................... .............................................................. 20 8.3.4 current sinks ........................................................................................................... .................................................................. 20 8.3.5 parameter ............................................................................................................... ................................................................... 20 8.4 charger............................................................................................................................................................................................... 22 8.4.1 soft charge/trickle charge .............................................................................................. ......................................................... 23 8.4.2 end of charge detection ................................................................................................. .......................................................... 23 8.4.3 vsupsw and temperature supervision...................................................................................... ............................................. 23 8.4.4 battery temperature supervision ......................................................................................... ..................................................... 23 8.4.5 no battery detection.................................................................................................... .............................................................. 23 8.4.6 charger modes .......................................................................................................... ................................................................ 24 8.4.7 parameter .............................................................................................................. .................................................................... 24 9 detailed description - system functions ............................................................................................................................. 26 9.1 system ............................................................................................................................................................................................ 26 9.1.1 power up/down conditions ....................................................................................................................................................... 26 9.1.2 start-up sequence ...................................................................................................... ............................................................... 26 9.2 hibernation ......................................................................................................................................................................................... 27 9.3 supervisor .......................................................................................................................................................................................... 27 9.3.1 vsup supervision ....................................................................................................... .............................................................. 27 9.3.2 vdd27 supervision ...................................................................................................... ............................................................. 27 9.3.3 junction temperature supervision ....................................................................................... ..................................................... 27 9.3.4 power rail monitoring ................................................................................................................................................................ 27 9.4 interrupt generation ............................................................................................................................... ............................................ 28 9.4.1 irq source interpretation .............................................................................................. ............................................................ 28 9.4.2 interrupt sources ....................................................................................................................................................................... 28 9.5 10-bit adc ......................................................................................................................................................................................... 29 9.5.1 input sources ............................................................................................................................................................................. 29 ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 4 - 70 as3606 as3607 2v2 data sheet - contents 9.5.2 parameter .............................................................................................................. .................................................................... 29 9.6 gpio pins .......................................................................................................................................................................................... 30 9.7 2-wire-serial control interface ............................................................................................................................... ............................ 31 9.7.1 protocol ............................................................................................................... ....................................................................... 31 9.7.2 parameter .............................................................................................................. .................................................................... 34 10 register definition ............................................................................................................................... ................................. 35 11 application information ............................................................................................................................... .......................... 62 11.1 pad cells .......................................................................................................................................................................................... 62 11.2 application schematics ............................................................................................................................... ..................................... 63 12 package drawings and markings ............................................................................................................................... .......... 65 13 ordering information ............................................................................................................................... .............................. 69 ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 5 - 70 as3606 as3607 2v2 data sheet - pin assignments 4 pin assignments figure 3. pin assignments (top view) ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 6 - 70 as3606 as3607 2v2 data sheet - pin assignments 4.1 pin descriptions note: pin description may change in preliminary data sheets. table 1. pin description for as3606/07 pin name pin number type description if not used as3606 as3607 vbatsw - 1 sup io battery switch terminal to be connected to the li-ion battery open vsupsw 1 2 sup io battery switch terminal to be connected to system supplies vsupx always needed vusb 2 3 sup in charger or usb bus power input open battemp 4 4 ana io li-ion charger battery temp. sensor input open extbatsw 3 5 ana out external battery switch gate driver output open vdd27 5 6 sup io ldo5 output default 2.7v always needed pvdd4 - 7 ana out ldo4 output open vsup5 6 8 sup in ldo3/4 & ldo5 pos. supply terminal, connect to vsupsw always needed pvdd3 7 9 ana out ldo3 output open pvdd2 8 10 ana out ldo2 output open pvdd1 9 11 ana out ldo1 output open vsup4 10 12 sup in ldo1/2 pos. supply terminal always needed vsup1 11 13 sup in cvdd1 step down pos. supply terminal always needed lxc1 12 14 dig out cvdd1 step down switch output to coil open cvdd1 13 15 ana in cvdd1 and feedback pin open curr2 14 16 ana io load current sink2 terminal open curr1 15 17 ana io load current sink1 terminal open lxsu 16 18 dig out dcdc step-up switch output to coil open fbsu 17 19 ana in dcdc step-up feed-back open gpio4 - 20 ana io general purpose io 4 open gpio2 18 21 ana io general purpose io 2 open gpio1 19 22 ana io general purpose io 1 open gpio3 - 23 ana io general purpose io 3 open cscl 20 24 dig in 2-wire serif clock input open csda 21 25 dig io 2-wire serif data i/o open pwrup 22 26 dig in power up input open xirq 23 27 dig out interrupt request output open xres 24 28 dig io reset output open dvdd 25 29 sup in digital periphery pos. supply terminal always needed vsup3 26 30 sup in cvdd3 step down pos. supply terminal vsupx lxc3 27 31 dig out cvdd3 step down switch output to coil open cvdd3 28 32 ana in cvdd3 and feedback pin open cvdd2 29 33 ana in cvdd2 and feedback pin open ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 7 - 70 as3606 as3607 2v2 data sheet - pin assignments lxc2 30 34 dig out cvdd2 step down switch output to coil open vsup2 31 35 sup in cvdd2 step down pos. supply terminal always needed vbatsw 32 36 sup io battery switch terminal to be connected to the li-ion battery open vss 33 37 sup io exposed pad: neg. supply terminal for all blocks always needed table 1. pin description for as3606/07 pin name pin number type description if not used as3606 as3607 ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 8 - 70 as3606 as3607 2v2 data sheet - absolute maximum ratings 5 absolute maximum ratings stresses beyond those listed in table 2 may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in electrical characteristics on page 9 is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. the device should be operated under recommended o perating conditions. table 2. absolute maximum ratings parameter min max units comments 5v pins -0.5 7.0 v applicable for pins vbatsw, vsupsw, vsup1/ 2/3/4/5, pwrup, gpio1/2/3/4, vbus 3v pins -0.5 5.0 v applicable for pins dvdd 30v pins -0.5 32 v applicable for pin lxsu, curr1/2 5v pins with protection to vsupx -0.5 7.0 vsupx+0.5 v applicable for pins extbatsw, fbsu 3v pins with protection to vdd27 -0.5 5.0 vdd27 v applicable for pins battemp 3v pins with protection to dvdd -0.5 5.0 dvdd+0.5 v applicable for pins xirq, xres, cscl, csda 3v pins with protection to vsupx -0.5 5.0 vsupx+0.5 v applicable for pins pvdd1/2/3/4, vdd27, cvdd1/2/3, lxc1,/2/3 input current (lat ch-up immunity) -100 100 ma norm: jedec 78 continuous power dissipation (t a = +85oc) continuous power dissipation 1w p t 1 for qfn32/36 package (r th ~ 30k/w) 1. depending on actual pcb layout and pcb used electrostatic discharge electrostatic discharge hbm 1.5 kv norm: jedec jesd22-a114c temperature ranges and storage conditions junction temperature +110 oc storage temperature range -55 +125 oc humidity non-condensing 585% temperature (soldering) package body temperature 260 oc norm ipc/jedec j-std-020 2 the lead finish for pb-free leaded packages is matte tin (100% sn) 2. the reflow peak soldering temperature (body temperature) is specified according ipc/jedec j-std-020 ?moisture/reflow sensitiv ity classification for nonhermetic solid state surface mount devices? moisture sensitive level 3 represents a max. floor live time of 168h ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 9 - 70 as3606 as3607 2v2 data sheet - electrical characteristics 6 electrical characteristics vsupx=+2.7v...+5.5v, t a =-40oc...+85oc. typical values are at vsupx=+3.6v, t a =+25oc, unless otherwise specified. table 3. electrical characteristics symbol parameter condition min typ max unit vbatsw battery supply voltage operation, vbus > 2.7v 0 3.6 5.5 v operation from battery 2.7 3.6 5.5 v vsupx supply voltage vsupsw, vsup1/2/3/4/5 2.7 3.6 5.5 v vbus usb vbus voltage operating, vsup5 > 2.7v 0 5.0 5.5 v charging 4.5 5.0 5.5 v dvdd digital periphery supply voltage 1.8 3.6 v vdd27 analog supply voltage 2.6 2.7 3.5 v v delta + difference of positive supplies vdd27-vsupx 0 v t amb operating temperature range -40 +85 oc i sd shut-down current @ vbatsw = 4.2v 600 na i q quiescent current all regulators off reference & ldo5 on 160 a io pins vid 3v 3v digital input pins xres, cscl, csda 0 3.6v or dvdd +0.5 v via 3v 3v input pin battemp 0 3.6v or vdd27 +0.5 v vi 5v 5v input pins gpio1/2/3/4 05.5vv vi 5v 5v input pin fbsu 0 5.5v or vsup5 +0.5 v vi 30v 20v analiog input pins lxsu, curr1/2 030v por & watchdog v por_on power-on reset activation level power-on reset activation level when vdd27 decreases 2.15 v v por_off power-on reset release level power-on reset release when vdd27 increases 2.0 v v por_hy power-on hysteresis 100 mv pwrup t on_delay delay time of pin pwrup minimum key press time 60 ms v pwrup_l input level low pin pwrup, vsup5>3v 0.5 v v pwrup_h input level high pin pwrup, vsup5>3v vsup5/3 v pin pwrup, vsup5<=3v 1 v i pwrup internal pull-down current source pin pwrup; @2.7v 10 20 30 a ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 10 - 70 as3606 as3607 2v2 data sheet - electrical characteristics digital inputs/outputs v do_dl digital output driver capability (drive low) pins xres, xirq, gp iox @ 6ma, open drain mode 20% dvdd v i pu internal pull-up current source pins xirq @ 0v 13 a pins csda, cscl @ 0v 100 a i pd internal pull-down current source pins gpiox @ 2.7v 8 13 20 a v di_l digital input level low pin gpiox 30% dvdd v v di_h digital input level high pin gpiox 70% dvdd v table 3. electrical characteristics (continued) symbol parameter condition min typ max unit ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 11 - 70 as3606 as3607 2v2 data sheet - typical operating characteristics 7 typical operating characteristics vsupx = +3.6v, ta = +25oc, unless otherwise specified. ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 12 - 70 as3606 as3607 2v2 data sheet - detailed description - power m anagement functions 8 detailed description - power management functions 8.1 low drop out regulators these ldos are designed to supply sensitive analog circuits, audi o devices, ad and da converters, micro-controller and other pe ripheral devices. the design is optimized to deliver the best compromise between quiescent current and regulator performance for battery powered devices. stability is guaranteed with ceramic output capacitors of 1f 20% (x5r) or 2.2f +100/-50% (z5u). the low esr of these caps en sures low output impedance at high frequencies. regulation performance is excellent even under low dropout conditions, when the power tra nsistor has to operate in linear mode. power supply rejection is high enough to suppress high ripple on the battery at the output. the low noi se performance allows direct connection of noise sensitive circuits without additional filtering networks. the low impedance of the power devi ce enables the device to deliver up to 150ma even at nearly discharged batteries without any decrease of performance. figure 4. ldo block diagram 8.1.1 ldo5 this ldo generates the digital supply voltage used for the pmu itself. input voltage is vsup5 output voltage is vdd27 (typ. 2.7v), this ldo always starts at the beginning of the start-up sequence as it is needed for all f urther operation. the default voltage cannot be changed in the boot rom. driver strength: 100ma, can be programmed to 200ma it is set to a default output voltage of 2.7v, 100ma max . it supplies the analog and digital part of the pmu. additional external loads are possible but must not exceed the supply ratings in total together with the operating internal blocks. further, the external load must no t induce noise to the vdd27. ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 13 - 70 as3606 as3607 2v2 data sheet - detailed description - power m anagement functions 8.1.2 ldo 1, ldo2, ldo3 & ldo4 these ldos can be used to generate the periphery voltage for the digital processor or other external components (e.g. ext. dac, usb-phy, sd- cards, nand-flashes, fm-tuner ?). ldo4 is only available on as3607. input voltage vsup5 for ldo3 and ldo4, and vsup4 for ldo2 and ldo1 output voltage is pvdd1, pvdd2, pvdd3 & pvdd4 (1.2v to 3.5v) default value at start-up is defined by the boot rom, when the boot rom is not programmed the ldos will not start-up driver strength: 150ma, can be programmed to 250ma 8.1.3 parameter vsupx=3.6v, t a = 25oc, unless otherwise specified. table 4. ldo parameter symbol parameter condition min typ max unit r on on resistance 1 psrr power supply rejection ratio f=1khz 70 db f=100khz 40 i off shut down current 100 na i vdd supply current without load 50 a low power enabled, without load 32 a noise output noise 10hz < f < 100khz 50 v rms t start startup time 200 s v out_tol output voltage tolerance minimum 50mv -2.5% 2.5% mv v linereg line regulation static <1 mv transient; slope: t r =10s <10 v loadreg load regulation static <1 mv transient; slope: t r =10s <10 i limit current limitation default 190 ma has to be enabled via register 350 ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 14 - 70 as3606 as3607 2v2 data sheet - detailed description - power m anagement functions figure 5. ldo characteristics transient load: 1ma ? 100maslope: 1s output load: 150ma load regulation output noise output load: 10ma transient input voltage ripple: 500mv output load: 150ma transient input voltage ripple: 500mv load regulation load regulation ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 15 - 70 as3606 as3607 2v2 data sheet - detailed description - power m anagement functions 8.2 dcdc step-d own converter these converters are meant to convert the battery voltage down to voltages which fit to the core and peripheral supply voltage requirements for microprocessors. input voltage vsup1/2/3 (usually connected to vsupsw) output voltage cvdd1 & cvdd2 & cvdd3 output voltage levels can be programmed independently form 0.61v to 3.35v the default value at start-up is defined by the boot rom dvm for all three outputs with selectable timings driver strength 700ma, dcdc2 & 3 can be combined together to double the output current under- and over-voltage detection high efficiency current force mode 1mhz or 2mhz switching frequency fast regulation mode figure 6. dcdc step-down block diagram ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 16 - 70 as3606 as3607 2v2 data sheet - detailed description - power m anagement functions 8.2.1 functional description the step-down converter is a high efficiency fixed frequency current mode regulator. by using low resistance internal pmos and nmos switches efficiency up to 97% can be achieved. the fast switching frequency allows using small inductors, without increasing the current ripple. the unique feedback and regulation circuit guarantees optimum load and line regulation over the whole output voltage range, up to a n output current of 700ma, with an output capacitor of only 10f. the implemented current limitation protects the dcdc and the coil during overl oad condition. to achieve optimized performance in different applications, adjustable settings allow to compromise between high efficiency and low input, output ripple: low ripple, low noise operation (current force mode = off). in this mode there is no minimum coil current necessary before switching off the pmos. as result, the on time of the pmos will be reduced down to tmin_on at no or light load conditions, even if the coil current is very small or the coil current is inverted. this results in a very low ripple and noise, but decreased efficiency, a t light loads, especially at low input to output voltage differences. in the case of an inverted coil current the regulator will not operate in pulse skip m ode. figure 7. dcdc buck with disabled current force / pulse skip mode high efficiency operation (c urrent force mode = on). in this mode, there is a minimum coil current necessary before switching off the pmos. as result, fewer pulses at low output loads are necessary, and therefore the efficiency at low output load is increased. on the other hand the output voltage ripple increases, and the noisy pulse skip operation is on up to a higher output current. figure 8. dcdc buck with enable d current force / pulse skip mode it?s also possible to switch between these two modes dynamically during operation. 1: lxc1 voltage 2: coil current (1mv=1ma) 3: output voltage 1: lxc1 voltage 2: coil current (1mv=1ma) 3: output voltage ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 17 - 70 as3606 as3607 2v2 data sheet - detailed description - power m anagement functions dvm (dynamic voltage management). to minimize the over-/undershoot during a change of the output voltage, the dvm can be enabled. with dvm the output voltage will ramp up/down with a selectable slope after the new value was written to the registers. without dvm the slew rate of the output voltage is only determined by external components like the coil and load capacitor as well as the load curre nt. fast regulation mode. this mode can be used to react faster on sudden load changes and thus minimize the over-/undershoot of the output voltage. frm needs an 22uf output capacitor instead the 10uf one to guarantee the stability of the regulator. low frequency operation. especially for very low load conditions, e.g. during a sleep mode of a processor, the switching frequency can be reduced to achieve a higher efficiency. 100% pmos on mode for low dropout regulation. for low input to output voltage difference the dcdc converter can use 100% duty cycle for the pmos transistor, which is than in ldo mode. 8.2.2 parameter vsup=3.6, t a = 25oc, unless otherwise specified. table 5. dcdc parameter symbol parameter condition min typ max unit v in input voltage vsupx 2.7 5.5 v v out regulated output voltage 0.6125 3.35 v v out_tol output voltage tolerance minimum 50mv -3% 3% mv i load maximum load current 600 700 ma i limit current limit 1000 ma r psw p-switch on resistance vsupx=3.0v 0.5 0.7 r nsw n-switch on resistance vsupx=3.0v 0.5 0.7 f sw switching frequency depending on dcdc_cntr settings 1/2 mhz f swsc switching frequency in shortcut case 0.6 mhz c out output capacitor ceramic, 10% tolerance 10 f lx inductor 10% tolerance 2.2 h eff efficiency iout=150ma, vout=3.0v 97 % i vdd current consumption operating current without load shutdown current 65 0.1 a t min_on minimum on time 80 ns t min_off minimum off time 40 ns v linereg line regulation static 2 mv transient; slope: t r =10s, 100mv step, 200ma load 10 v loadreg load regulation static 5 mv transient; slope: t r =10s, 100ma step 50 ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 18 - 70 as3606 as3607 2v2 data sheet - detailed description - power m anagement functions figure 9. dcdc step-down performance characteristics dcdc buck efficiency @2mhz, 3.6v vsupx 60,00 65,00 70,00 75,00 80,00 85,00 90,00 95,00 100,00 1 10 100 1000 output current [ma] efficiency [%] cvdd1 @ 1,2v vout cvdd1 @ 1,8v vout cvdd1 @ 3v vout output voltage vs. output current 1,175 1,185 1,195 1,205 1,215 1,225 0 50 100 150 200 250 output current [ma] output voltage [v] ? v in =3.6v line regulation 1,195 1,2 1,205 1,21 1,215 3 3,4 3,8 4,2 4,6 5 input voltage [v] output voltage [v] ? v out =1.2v i out =0ma i out =125ma i out =250ma ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 19 - 70 as3606 as3607 2v2 data sheet - detailed description - power m anagement functions 8.3 30v step-up dcdc converter the integrated step-up dc/dc converter is a high efficiency current-mode pwm regulator, providing an output voltage up to 30v. a constant switching-frequency results in a low noise on supply and output voltages. it has two programmable high voltage current sinks (0 to 38.25ma) for driving e.g. white leds as back-light. it can drive also unbalanced strings due to the internal automatic feedback selection. a voltage feedback mode allows generating constant supply voltages for e.g. oleds. the output voltage is set by an external res istor divider and an internal current sink. an internal protection circuit will shut down the regulator if the voltage on fbsu exceeds the over voltage threshold. no more external protection has to be used to avoid an exceeding of the operation conditions in a no load situation. figure 10. dcdc15 block diagram 8.3.1 voltage feedback setting bit su_curr_fb = 0 enables voltage feedback at pin fbsu. the output voltage is regulated to a constant value, given by (bit su_gain should be set to 1 in this configuration) u step up_out = (r 1 +r 2 )/r 2 *1.25 + i fb * r 1 (eq 1) if r2 is not used, the output voltage is by (bit su_gain should be set to 0 in this configuration) u step up_out = 1.25 + i fb * r 1 (eq 2) where: u step up_out = step up dc/dc converter output voltage r 1 = feedback resistor r1 r 2 = feedback resistor r2 i fb = tuning current at pin fbsu; 0 to 31a ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 20 - 70 as3606 as3607 2v2 data sheet - detailed description - power m anagement functions note: the voltage on curr1 and curr2 must not exceed 30v. 8.3.2 over voltage protection (ovp) setting bit su_curr_fb = 1 enables feedback via the current sink pins. the voltage on the current sink pin is regulated to vcurr . the selection of the current sink with the larger load is done automatically. the pin fbsu acts as an overvoltage protection in thi s mode. please be sure to set the voltage to a higher level than needed to drive the longer led string. the calculation of the resistor can be done the same as described in the chapter above. 8.3.3 dls & dimming as3606/07 feature external dimming inputs via curr1, curr2, gpio1 or gpio2 by directly connecting a pwm output of e.g. the disp lay controller for dls (dynamic luminance scaling). manual dimming can be done at any time by setting the sink current via i2c comm ands. 8.3.4 current sinks the current sinks work independent from each other and can also be used without the booster, or can act as a dimming input if t hey are not needed as a sink. table 6. voltage feedback example values idcdc_fb u step up_out u step up_out a r1 = 1m , r2 not used r1 = 500k , r2 = 50k 0-1 3 . 7 5 1-1 4 . 2 5 2-1 4 . 7 5 3-1 5 . 2 5 4-1 5 . 7 5 56 . 2 51 6 . 2 5 67 . 2 51 6 . 7 5 78 . 2 51 7 . 2 5 89 . 2 51 7 . 7 5 9 10.25 18.25 10 11.25 18.75 11 12.25 19.25 12 13.25 19.75 13 14.25 20.25 14 15.25 20.75 15 16.25 21.25 ??? 30 31.25 28.75 31 32.25 29.25 ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 21 - 70 as3606 as3607 2v2 data sheet - detailed description - power m anagement functions 8.3.5 parameter vsupx=3.6v, t a = 25oc, unless otherwise specified. figure 11. 30v step-up performance characteristics table 7. dcdc parameter symbol parameter condition min typ max unit v sw high voltage pin pin fbsu 0 30 v i vdd quiescent current pulse skipping mode 140 a v fb feedback voltage, transientt pin curr1 or curr2 0 30 v pin fbsu 0 5 v v fbsu feedback voltage, for voltage regulation pin fbsu 1.2 1.25 1.3 v v curr feedback voltage, for current sink regulation pin curr1 or curr2 0.4 0.5 0.6 v i dcdc_fb additional tuning current at pin dcdc_fb and over voltage protection adjustable by software using register dcdc control1 1a step size (0-31a) v protect = 1.25v + idcdc_fb * r 1 03 1 a accuracy of feedback current at full scale -6 6 % r sw switch resistance 1 i load load current @ 30v output voltage 0 50 ma f sw fixed switching frequency su_frequ = 0 1 mhz c out output capacitor ceramic, 20%. use nominal 4.7f capacitors to obtain at least 0.7f under all conditions (voltage dependence of capacitors) 0.7 4.7 f l inductor use inductors with small c parasitic (<100pf) for high efficiency 71013h t min_on minimum on-time guaranteed per design 100 190 ns mdc maximum duty cycle guaranteed per design 84 90 % dcdc boost 6 leds 55,00 60,00 65,00 70,00 75,00 80,00 85,00 90,00 1 10 100 output current [ma] efficiency (%) ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 22 - 70 as3606 as3607 2v2 data sheet - detailed description - power m anagement functions 8.4 charger this block can be used to charge a 4v li-ion accumulator. it supports constant current and constant voltage charging modes with adjustable charging currents (94 to 1000ma) and maximum charging voltage (3.9 to 4.25v). the charger consists basically of a pre-regulator, which limits the current from e.g. the usb input and provides a constant vsu p after reaching eoc (end of charge) and the battery switch, which is controlling the current into the battery. input voltage of the pre-regulator: vusb output of the pre-regulator and input for the battery switch and system supply: vsupsw output of the battery switch and battery terminal: vbatsw cvm (constant voltage), ccm (constant current) and trickle charging adjustable eoc voltage and eoc current limit selectable input -, trickle- and charging-current limit auto-resume with selectable resume voltage level charger time-out supervision with selectable time-out setting battery temperature supervision supporting two levels (45 or 50oc) and 100k or 10k ntc types no battery detection status register and interrupt generation per default the usb current limit is set to 470ma and the charger is switched off. the current battery and charger input voltage can be measured with the general purpose adc. figure 12. charger block diagram ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 23 - 70 as3606 as3607 2v2 data sheet - detailed description - power m anagement functions figure 13. charger states 8.4.1 soft charge/trickle charge if the battery and therefore vbatsw is below 3v the charger is working in a fixed soft charge mode with a smaller trickle charg ing current of 24- 265ma. after reaching the 3v level the charger switches to the constant current mode with the programmed charging current. 8.4.2 end of charge detection for the eoc level 4 presets can be selected. this makes it possible to monitor the charging progress also during constant voltage mode. if the eoc level is reached an interrupt can be generated, but it is also possible to poll the charger status bits at any time. 8.4.3 vsupsw and temperature supervision the charger will automatically reduce the charging current if vsupsw drops below the selected level. it will automatically stop charging when the chip temperature gets too to hot. the charger will return to normal operation as defined in the charger registers if vsupsw and the chip temperature return to their normal operating range. 8.4.4 battery temperature supervision this charger block also features a supply for an external ntc resistor to measure the battery temperature while charging. if th e temperature is too high (voltage on battemp pin is below vbattemp_on ) the charger will stop operation. if needed an interrupt can be generated based on this event. when the battery temperature drops the charger the voltage on battemp pin will rise above vbattemp_off and the charger will start charging again. this is forming a temperature hysteresis of about 3 to 5c to avoid an oscillation of the charger. the levels for switching off the charger (45oc or 55oc) as well as the type of ntc (10k or 100k) can be selected via register s ettings. the battery temperature supervision via the ntc can be switched off ( ntc_on = 0). the supply for the ntc will be only on when a charger is detected and ntc_on bit is set. 8.4.5 no battery detection if the charger state machine reaches eoc 2 times within a very short period it assumes that there is no battery connected to th e vbatsw terminal. after this a sensing current of 1ua is applied to the battemp pin to detect if a battery is reconnected. ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 24 - 70 as3606 as3607 2v2 data sheet - detailed description - power m anagement functions 8.4.6 charger modes figure 14. charger modes 8.4.7 parameter vdd27=2.7, t a = 25oc, unless otherwise specified. table 8. charger parameter symbol parameter condition min typ max unit i chg (0-7) charging current @ 470ma i nom -8% i nom i nom +8% ma v chg (0-7) charging voltage end of charge is true v nom -50mv v nom v nom +33mv v v on_abs charger on voltage detection rising edge on vusb start 0.8 v rising edge on vusb end 3.5v v v on_rel vusb-vbatsw 170 240 mv v off_rel vusb-vbatsw 50 mv v battemp_on battery temp. high level (45 or 55oc) vsup >3v ntc beta =4200 610 or 400 mv ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 25 - 70 as3606 as3607 2v2 data sheet - detailed description - power m anagement functions v battemp_off battery temp. low level (42 or 50oc) vsup >3v ntc beta =4200 700 or 500 mv i battemp ntc bias current 100k 10k 15 150 a i chg_off end of charge current level vsup >3v 8% 10% 15% 20% i nom ma i rev_off reverse current shut down vsupsw = 5v, vusb open <1 a r on_batsw battery switch on-resistance 0.15 table 8. charger parameter symbol parameter condition min typ max unit ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 26 - 70 as3606 as3607 2v2 data sheet - detailed description - system functions 9 detailed description - system functions 9.1 system the system block handles the power up, power down and regulator voltage settings of the pmu. 9.1.1 power up/down conditions the chip powers up when one of the following conditions is true: the chip automatically shuts off if one of the following conditions arises: 9.1.2 start-up sequence the start-up sequence is defined in the boot rom and will be fixed during the production test. the sequence and voltage of the regulators can be freely chosen for the start-up sequence with the following limitations: vdd27 will always start-up, after a ~5ms delay the sequencer will start-up the other chosen regulators with either 0, 1 or 4ms delay each. a maximum of 6 regulators (no matter of dcdc or ldo) or 5 regulators and a changed gpio configuration can be chosen for the sta rt-up. on a 7th time-slot pvdd2 can be started-up, but has reduced setting on the output voltage pwrgood will be activated ~3ms after the last regulator. xres will be released 10ms to 110ms (set in the boot rom) after the last regulator started up. table 9. power up conditions # source description 1 pwrup pwup on_key high level at pwrup pin of >= 1/3 vbatsw 2 vbus pwup usb plug-in ?. high level at vbus pin of >= 4.5v and >2.7v on vsup5 table 10. power down conditions # source description 1 serif major pwdn power-down by serif writing 0h to register 20h 2 emergency pwdn power-down if pwrup pin is high for 8sec. this has to be enabled in register 21h, per default a reset cycle is initiated. it can also be changed to 4s. 3 serif watch-dog pwdn write 3h to reg. 20h ? enable serif watch-dog power-down if no serif read is seen for 500ms. 4 junction-temp pwdn power-down if junction temperature rises up to 140degc. this threshold can be lowered with bits <4:0> in reg 21h. this supervisor can be disabled with bit 2 in reg. 20h. 5 vdd27 low pwdn power-down if vdd27 ldo5 has 10% under-voltage for more than 680s. this supervisor can get disabled with bit 6 in reg. 21h. 6 cvdd1 low pwdn power-down if enabled with bit 7 in reg. 23h and cvdd1 dcdc has 10% under-volta ge for more than 680s. 7 cvdd2 low pwdn power-down if enabled with bit 5 in reg. 23h and cvdd2 dcdc has 10% under-volta ge for more than 680s. 8 cvdd3 low pwdn power-down if enabled with bit 3 in reg. 23h and cvdd3 dcdc has 10% under-volta ge for more than 680s. 9 vsup low pwdn power-down if vsupx goes below the defined level in reg22h (bits <3:1>) this supervisor has to be enabled with bit 4 in reg. 22h. ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 27 - 70 as3606 as3607 2v2 data sheet - detailed description - system functions 9.2 hibernation hibernation allows shutting down a part or the complete system. hibernation can be terminated by every possible interrupt of the pmu. the interrupt has to be enabled before going to hibernation. 9.3 supervisor this supervisor function can be used for automatic detection of vsup brown out or junction over-temperature condition. 9.3.1 vsup supervision the vsup supervision has a selectable level. if the shutdown is not enabled an interrupt can be generated. 9.3.2 vdd27 supervision if vdd27 reaches the ?programmed level of vdd27? -10% for typ. 3ms, the pmu shuts down automatically. if the shutdown is not en abled an interrupt can be generated. 9.3.3 junction temperature supervision the temperature supervision level can also be set by 5 bits (120 to ?15oc). if the temperature reaches this level, an interrupt can be generated. the over-temperature shutdown level is always 20oc higher. this shutdown can be disabled in reg. 20h. 9.3.4 power rail monitoring the 3 dcdc regulators have an extra monitor which observes the output voltage of the regulators. this power rail monitors are i ndependent from the 10bit adc. to activate these please see related registers. for a shut down the voltage of the regulator has to be 10% or more below the programmed value for more than 3ms. table 11. hibernation state description enter via gpio to enter hibernation mode the following settings have to be done: - enable just these irq sources which should lead to leave hibernation mode. - make sure that irq is inactive (irq flags get cleared by reg 23h-26h readings. - set the gpio to input - select the gpio for hibernation control ( gpio_dimm_hbn_sel <1:0> ) - enable hibernation via gpio ( gpio_hbn_on ) - define which regulators should be kept powered a nd enter hibernation by writing to reg 1ch_0x04 + reg 17h-4. this register must not be read back!!! - drive the selected gpio to low. note that hibernation will shutdown regulators which are not in the keep list of the mentioned reg 17h-4 writing and are part of the power-up sequence. enter via sw to enter hibernation mode the following settings have to be done: - enable just these irq sources which should lead to leave hibernation mode. - make sure that irq is inactive (irq flags get cleared by reg 23h-26h readings. - set a delay for entering hibernation if needed ( hbn_delay<1:0> ) - define which regulators should be kept powered a nd enter hibernation by writing to reg 1ch_0x04 + reg 17h-4. this register must not be read back.!!! note that hibernation will shutdown regulators which are not in the keep list of the mentioned reg 17h-4 writing and are part of the power-up sequence. hibernation vdd27 chip supply is kept on all other regulators are switched off dependent on the keep-bits xres goes active (can be disabled in the boot rom) and pwrgood goes inactive leave the chip will come out of hibernation with - irq activation or -gpio control start-up sequence is provided defined by the boot rom. ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 28 - 70 as3606 as3607 2v2 data sheet - detailed description - system functions 9.4 interrupt generation all interrupt sources can get enabled or disabled by corresponding bits in the 4 irq-bytes. by default no interrupt source is e nabled. the xirq pin can be configured to operate in push/pull (2 different driver strengths), open-drain mode or to be tri-state. the signal polarity can be defined as active-low or active-high. default state is open-drain active-low. 9.4.1 irq source interpretation there are 3 different modules to process interrupt sources: level. the irq output is kept active as long as the interrupt source is present and this irq-bit is enabled. edge. the irq gets active with a high going edge of this source. the irq stays active until the corresponding irq-register gets read. status change. the irq gets active when the source-state changes. the change bit and the status can be read to notice which interrupt was the source. the irq stays active until the corresponding interrupt register gets read.de-bouncer there is a de-bounce function implemented, a de-bounce time of 3ms is selected per default in the irq_enrd_3 register (26h). 9.4.2 interrupt sources these irq events will activate the xirq pin: 10bit adc end of conversion charger end of charge, connect/disconnect, no battery battery temperature high (at 45oc or 50oc with 100/10k ntc) junction temperature high battery low (brown-o ut voltage reached) power-up key (pin pwrup) pressed current sink low voltage power rail monitor: over-voltage cvdd1, cvdd2, cvdd3 power rail monitor: under-volt age cvdd1, cvdd2, cvdd3, vdd27 ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 29 - 70 as3606 as3607 2v2 data sheet - detailed description - system functions 9.5 10-bit adc this general purpose adc can be used for measuring several voltages and currents to perform functions like battery monitor, tem perature supervision, button press detection, etc. 9.5.1 input sources 9.5.2 parameter vdd27=2.7, t a = 25oc, unless otherwise specified. table 12. adc10 input sources # source range lsb description 0 vsup 5.120v 5mv check main system supply voltage 1 gpio3 5.120v 5mv 2 gpio4 5.120v 5mv 3 vbatsw 5.120v 5mv check battery voltage of 4v li-ion accumulator 4 vusb 5.120v 5mv check usb/charger input voltage 5 5.120v 5mv source defined by dc_test in register 18h 6 battemp 2.048v 2mv check battery charging temperature 7 gpio1 5.120v 5mv 8 gpio2 5.120v 5mv 9 pwrup 5.120v 5mv a 2mv reserved b 2mv reserved c vbe_1a 1.024 1mv measuring basis-emitter voltage of temperature sense transistor; tj = (674 - adc10<9:0>) / 2 d vbe_2a 1.024 1mv measuring basis-emitter voltage of temperature sense transistor; tj = (694 - adc10<9:0>) / 2 e 1mv reserved f 1mv reserved table 13. adc10 parameter symbol parameter condition min typ max unit adc fs adc full scale range 2.16 v t con conversion time -3450s ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 30 - 70 as3606 as3607 2v2 data sheet - detailed description - system functions 9.6 gpio pins as3607 features 4 gpio pins, as3606 has 2 gpio pins. if not re-configured in the start-up sequence gpio1, gpio3 and gp io4 are input per default.gpio2 is set to output and the pin i s driven to low right at the beginning of the startup sequence. gpio3/4 have one state defined as input and three states as output. the followi ng table shows the different input/output options. when configured as input the following functionality is available: adc input, to measure external voltage sources wake-up input to return from hibernation hibernation enable input (gpio1/2/3 only) pwm dimming input (gpio1/2/3 only) gpio pins have a 200kohm pull-down resistor activa ted when they are used as an input. (hiz-mode). please note that all gpio pins are open-drain outputs. they c an only output a logic ?high? if a pull-up and the corresponding p ull-up voltage is present. table 14. gpio configuration gpio1 gpio2 gpio4/3 00 xcharging (1hz pulses) low hiz / hiz (input) 01 xvsup_low xvsup_low xvsup_lo w / xcharging (1hz pulses) 10 xpwrup high xpwrup / pwrgood 11 pwrgood xcharging (1hz pulses) xeoc / xcharger_active table 15. gpio output functions function description xcharging (1hz pulses) the output will be high when the charger is no active. the output toggles between high and low as long as the charging is on going. if eoc, a timeout or overtempertur event stops the charger the output stops toggling. xcharger_active the output will be high when the charger is no active or in eoc; it will be low if the charger is active. xeoc the output will be high when the charger active; it will be low if the charger is has reached eoc. the output will return back to high if the charger enters resume state. xpwrup the output will get low if the pwrup pin is high. pwrgood the output will be high about 3ms after the start-up seuence is finished. it will be low during the sequence. please be sure to configure the gpio before the pull-up voltage, otherwise the output will be high as long as the gpios are default inputs. xvsup_low the output will get low if the vsup undervoltage level is reached. high the output will be high. low the output will be low. ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 31 - 70 as3606 as3607 2v2 data sheet - detailed description - system functions 9.7 2-wire-serial control interface there is an i2c slave block implemented to have access to 64 byte of setting information. the i2c address is: adr_group8 - audio processors 8ch_write 8dh_read 9.7.1 protocol figure 15. byte write table 16. 2-wire serial symbol definition symbol definition rw note s start condition after stop r 1 bit sr repeated start r 1 bit dw device address for write r 1000 1100b (8ch) dr device address for read r 1000 1101b (8dh) wa word address r 8 bit a acknowledge w 1 bit n no acknowledge r 1 bit reg_data register data/write r 8 bit data (n) register data/read w 8 bit p stop condition r 1 bit wa++ increment word address internally r during acknowledge as3606 as3607 (=slave) receives data as3606 as3607 (=slave) transmits data s dw a wa a reg_data a p write register wa++ ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 32 - 70 as3606 as3607 2v2 data sheet - detailed description - system functions figure 16. page write byte write and page write formats are used to write data to the slave. the transmission begins with the start condition, which is generated by the master when the bus is in idle state (the bus is free). the device- write address is followed by the word address. after the word address any number of data bytes can be sent to the slave. the wo rd address is incremented internally, in order to write subsequent data bytes on subsequent address locations. for reading data from the slave device, the master has to change the transfer direction. this can be done either with a repeate d start condition followed by the device-read address, or simply with a new transmission start followed by the device-read address, when the bus is in idle state. the device-read address is always followed by the 1st register byte transmitted from the slave. in read mode any number of subsequent register bytes can be read from the slave. the word address is incremented internally. figure 17. random read random read and sequential read are combined formats. the repeated start condition is used to change the direction after the da ta transfer from the master. the word address transfer is initiated with a start condition issued by the master while the bus is idle. the start condition i s followed by the device-write address and the word address. in order to change the data direction a repeated start condition is issued on the 1st scl pulse after the acknowledge bit of th e word address transfer. after the reception of the device-read address, the slave becomes the transmitter. in this state the slave transmits register data located by the previous received word address vector. the master responds to the data byte with a not-acknowledge, and issues a stop co ndition on the bus. s dw a wa a reg_data 1 a p write register wa++ reg_data 2 a write register wa++ reg_data n a write register wa++ ... s dw a wa a n a read register wa++ data sr dr p ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 33 - 70 as3606 as3607 2v2 data sheet - detailed description - system functions figure 18. sequential read sequential read is the extended form of random read, as more than one register-data bytes are transferred subsequently. in diff erence to the random read, for a sequential read the transferred register-data bytes are responded by an acknowledge from the master. the num ber of data bytes transferred in one sequence is unlimited (consider the behavior of the word-address counter). to terminate the transmissi on the master has to send a not-acknowledge following the last data byte and generate the stop condition subsequently. figure 19. current address read to keep the access time as small as possible, this format allows a read access without the word address transfer in advance to the data transfer. the bus is idle and the master issues a start condition followed by the device-read address. analogous to random read, a single byte transfer is terminated with a not-acknowledge after the 1st register byte. analogous to sequential read an unlimited number of data bytes can be transferred, where the data bytes has to be responded with an acknowledge from the master. for termination of the transmissi on the master sends a not-acknowledge following the last data byte and a subsequent stop condition. s dw a wa a n a read register wa++ data sr dr p reg_data 2 a read register wa++ reg_data n ... a read register wa++ s n a read register wa++ data dr p reg_data 2 a read register wa++ reg_data n ... a read register wa++ ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 34 - 70 as3606 as3607 2v2 data sheet - detailed description - system functions 9.7.2 parameter figure 20. 2-wire serial timing dvdd =2.9v, t amb =25oc, unless otherwise specified. table 17. 2-wire serial parameter symbol parameter condition min typ max unit v csl cscl, csda low input level (max 30%dvdd) 0 - 0.87 v v csh cscl, csda high input level cscl, csda (min 70%dvdd) 2.03 - 5.5 v hyst cscl, csda input hysteresis 200 450 800 mv v ol csda low output level at 3ma - - 0.4 v tsp spike insensitivity 50 100 - ns t h clock high time max. 400khz clock speed 500 ns t l clock low time max. 400khz clock speed 500 ns t su csda has to change tsetup before rising edge of cscl 250 - - ns t hd no hold time needed for csda relative to rising edge of cscl 0--ns ts csda h hold time relative to csda edge for start/stop/rep_start 200 - - ns t pd csda prop delay relative to lowgoing edge of cscl 50 ns 8 1-7 cscl csda 8 9 8 1-7 8 9 8 1-7 8 9 start condition address r/w ack data ack data ack stop condition ts t su t h t l t hd t pd ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 35 - 70 as3606 as3607 2v2 data sheet - register definition 10 register definition table 18. i2c register overview addr name b7 b6 b5 b4 b3 b2 b1 b0 pmu register 17h-1 cvdd1 cvdd1_fast 0: cext=10f 1: cext=22f vsel_cvdd1<6:0> 0 ? off 0x01 ? 0x40: 0.6v + vsel * 12.5mv -> (0.6125v ? 1.400v) 0x41 ? 0x70: 1.4v + (vsel-0x4 0) * 25mv ->(1.425v ? 2.600v) 0x71 ? 0x7f: 2.6v + (vsel-0x70) * 50mv -> (2.650v ? 3.350v) 17h-2 cvdd2 cvdd2_fast 0: cext=10f 1: cext=22f vsel_cvdd2<6:0> 0 ? off 0x01 ? 0x40: 0.6v + vsel * 12.5mv -> (0.6125v ? 1.400v) 0x41 ? 0x70: 1.4v + (vsel-0x4 0) * 25mv ->(1.425v ? 2.600v) 0x71 ? 0x7f: 2.6v + (vsel-0x70) * 50mv -> (2.650v ? 3.350v) 17h-3 cvdd3 cvdd3_fast 0: cext=10f 1: cext=22f vsel_cvdd3<6:0> 0 ? off 0x01 ? 0x40: 0.6v + vsel * 12.5mv -> (0.6125v ? 1.400v) 0x41 ? 0x70: 1.4v + (vsel-0x4 0) * 25mv ->(1.425v ? 2.600v) 0x71 ? 0x7f: 2.6v + (vsel-0x70) * 50mv -> (2.650v ? 3.350v) 17h-4 hibernation - keep_pvdd4 keep_pvdd3 keep_pvdd2 keep_pvdd1 keep_cvdd3 keep_cvdd2 keep_cvdd1 17h-5 dcdc_cntr cfm_cvdd23_of f 0: pulse skip on 1: pulse skip off cfm_cvdd1_off 0: pulse skip on 1: pulse skip off cvdd23_freq 0: 2mhz 1: 1mhz cvdd1_freq 0: 2mhz 1: 1mhz dvm_cvdd23<1:0> 0: immediate; 1: 42s/step; 2: 166s/step; 3: 666s/step dvm_cvdd1<1:0> 0: immediate; 1: 42s/step; 2: 166s/step; 3: 666s/step 17h-7 gpio_cntr mux_gpio43<1:0> 0: hiz/hiz; 1: xvsup_low/xcharging; 2: xpwrup/pwrgood; 3: xeoc/xcharger_active drive_gpio2 0: opend drain 1: hiz mux_gpio2<1:0> 0: low; 1: xvsup_low; 2: high; 3: xcharging drive_gpio1 0: hiz 1: opend drain mux_gpio1<1:0> 0: xcharging; 1: xvsup_low; 2: xpwrup; 3: pwrgood 18h-1 pvdd1 pvdd1_on ilim_h_pvdd1 0: 150ma 1: 250ma lp_pvdd1 0: normal mode 1: low power mode vsel_pvdd1<4:0> 0x00 ? 0x0f: 1.2v + vsel * 50mv (1.2v ? 1.95v) 0x10 ? 0x1f: 2.0v + (vsel-0x10) * 100mv (2.0v ? 3.5v) 18h-2 pvdd2 pvdd2_on ilim_h_pvdd2 0: 150ma 1: 250ma lp_pvdd2 0: normal mode 1: low power mode vsel_pvdd2<4:0> 0x00 ? 0x0f: 1.2v + vsel * 50mv (1.2v ? 1.95v) 0x10 ? 0x1f: 2.0v + (vsel-0x10) * 100mv (2.0v ? 3.5v) 18h-3 pvdd3 pvdd3_on ilim_h_pvdd3 0: 150ma 1: 250ma lp_pvdd3 0: normal mode 1: low power mode vsel_pvdd3<4:0> 0x00 ? 0x0f: 1.2v + vsel * 50mv (1.2v ? 1.95v) 0x10 ? 0x1f: 2.0v + (vsel-0x10) * 100mv (2.0v ? 3.5v) ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 36 - 70 as3606 as3607 2v2 data sheet - register definition 18h-4 pvdd4 pvdd4_on ilim_h_pvdd4 0: 150ma 1: 250ma lp_pvdd4 0: normal mode 1: low power mode vsel_pvdd4<4:0> 0x00 ? 0x0f: 1.2v + vsel * 50mv (1.2v ? 1.95v) 0x10 ? 0x1f: 2.0v + (vsel-0x10) * 100mv (2.0v ? 3.5v) 18h-5 vdd27 prg_vdd27 0: boot rom 1:register defined ilim_h_vdd27 0: 100ma 1: 200ma lp_vdd27 - vsel_vdd27<3:0> 0x0 ? 0x2: 2.3v 0x3 ? 0xf: 2.0v + vsel* 100mv (2.3v ? 3.5v) 19h-0 chg_cntr bat_det_off auto_r esume bat_charge_on usb_currlim <3:0> 0: 94ma; 1: 141ma; 2: 189ma; 3: 237ma; 4: 285ma; 5: 332ma; 6: 380ma; 7: 428ma; 8: 470ma; 9: 517ma; a: 599ma; b: 760ma; c: 882ma; d: 1060ma; e-f: not defined usb_prereg_on 19h-1 chg_vcntr chg_v_resume <2:0> 0: 3.85v; 1: 3.9v; 2: 3.95v; 3: 4.0v; 4: 4.05v; 5: 4.1v; 6:4.15v; 7: 4.2v vsup_min<1:0> 0: 3.9v; 1: 3.6v; 2: 4.2v; 3: 4.5v chg_v_eoc <2:0> 0: 3.9v; 1: 3.95v; 2: 4.0v; 3: 4.05v; 4: 4.1v; 5: 4.15v; 6: 4.2v; 7: 4.25v 19h-2 chg_icntr chg_i_constant <3:0> 0: 94ma; 1: 141ma; 2: 189ma; 3: 237ma; 4: 285ma; 5: 332ma; 6: 380ma; 7: 428ma; 8: 470ma; 9: 517ma; a: 599ma; b: 760ma; c: 882ma; d: 1060ma; e-f: not defined chg_i_trickle <3:0> 0: 25ma; 1: 35ma; 2: 47ma; 3: 59ma; 4: 71ma; 5: 83ma; 6: 95ma; 7: 107ma; 8: 118ma; 9: 129ma; a: 150ma; b: 190ma; c: 221ma; d: 265ma; e-f: not defined 19h-3 chg_conf - chg_i_eoc<1:0> 0: 8%; 1: 15%; 2: 10%; 3: 20% vsup_eoc <2:0> 0: 4.3v; 1: 4.4v; 2: 4.5v; 3: 4.6v; 4: 4.7v; 5: 4.8v; 6: 4.9v; 7: 5.0v 19h-4 chg_ntc - ntc_mode 0: 55c; 1: 45c ntc_10k 0: 100k; 1: 10k; ntc_on 19h-5 chg_time - tmax_timer chg_timeout <3:0> 0:disabled; 1: 0.5h; 2: 1h; 3: 1,5h; 4: 2h; 5: 2.5h; 6: 3h; 7: 3.5h; 8: 4h; 9: 4.5h; a: 5h; b: 5.5h; c: 6h; d: 6.5h; e: 7h; f:7.5h 19h-6 chg_stat1 no_bat battemp_high eoc cv trickle resume cc chg_det 19h-7 chg_stat2 - batsw_mode <1:0> 1ah-1 out_cntr dcdc23_1.4a gpio_hbn_on hbn_delay<1:0> 0: 0ms; 1: 8ms; 2: 16ms; 3: 32ms drive_xirq<1:0> 0: 6ma od; 1: 6ma pp; 2: 1ma pp; 3: hiz mux_xirq<1:0> 0: xirq; 1: clkint1; 2: clkint2; 3: irq 1ah-2 clk_cntr clkint2<1:0> 0: low; 1: clk1hz (charger); 2: do not use; 3: high clkint1<1:0> 0: 2mhz; 1: 1mhz; 2: 1khz; 3: 125hz gpio_dimm_hbn_sel <1:0> 0: low; 1: gpio1; 2: gpio2; 3: gpio3 - 1bh-1 boost_cntr1 su_on - su_slowdim 0: tbd 1: tbd su_extdim<1:0> 0: no dimm; 1: curr1; 2: curr2; 3: gpio1/2/3 su_ovp_off su_curr_fb su_fastskip 1bh-2 boost_cntr2 su_ifb<4:0> 0x00 - 0x1f: 1a * su_ifb; su_currlim su_gain su_freq table 18. i2c register overview addr name b7 b6 b5 b4 b3 b2 b1 b0 ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 37 - 70 as3606 as3607 2v2 data sheet - register definition 1bh-3 curr1 icurr1<7:0> 0x00 - 0xff: 150a * icurr; 1bh-4 curr2 icurr2<7:0> 0x00 - 0xff: 150a * icurr; 1ch pmu_enable dc_test_mux <3:0> 0: open; 1: pvdd1; 2: pvdd2; 3: pvdd3; 4: pvdd4; 5: vdd27; 6: cvdd1; 7: cvdd2; 8: cvdd3; 9-f: not defined pmu_gate pmu_enable <2:0> subregister addresses for registers: 0x17: dcdc regulators 0x18: ldos regulators 0x19: charger 0x1a: io_clock_control 0x1b: backlight_dcdc system register 20h system design_version<3:0> - jtemp_sup_off i2c _wd_on pwr_hold 21h supervisor1 pwrup_sd_xres <1:0> 0: xres; 1: -; 2: sd; 3: sd sd_xres_time 0: 8s; 1: 4s jtemp_sup<4:0> temp_shutdown = 140oc - jtemp_sup*5oc (140oc...5oc) temp_irq = 120oc - jtemp_sup*5oc (120oc...-15oc) 22h supervisor2 - - vdd27low_sd_of f vsuplow_sd_on vsuplow_sup <2:0> vsuplow_sup_off 23h irqenrd_0 cvdd1_sd cvdd1_irq cvdd2_sd cvdd2_irq cvdd3_sd cvdd3_irq - cvdd1_under cvdd1_over cvdd2_under cvdd2_over cvdd3_under cvdd3_over - 24h irqenrd_1 pwrup_irq gpio1_irq gpio2_irq gpio3_irq gpio4_irq 25h irqenrd_2 chg_temp_irq chg_eoc_irq chg_nobat_irq chg_de t_irq - icurr_lv_irq vsup_low_irq vdd27_low_irq chg_temp chg_eoc chg_nobat chg_det 26h irqenrd_3 t_deb<1:0> 0: 3ms; 1: off; jtemp_high - adc_eoc 2eh adc10_0 adc10_mux<3:0> 0: vsup; 1: gpio3; 2: gpio4; 3: vsupsw; 4: vusb 5: dc_test; 6: battemp; 7: gpio1; 8: gpio2; 9: pwrup; a,b: -; c: vbe_1a; d: vbe_2a; e,f: - -- adc10<9:8> 2fh adc10_1 adc10<7:0> table 18. i2c register overview addr name b7 b6 b5 b4 b3 b2 b1 b0 ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 38 - 70 as3606 as3607 2v2 data sheet - register definition table 19. cvdd1 register name base default cvdd1 2-wire serial 00h offset: 17h-1 cvdd1 dc/dc buck regulator control register this is an extended register and needs to be enabled by writing 001b to reg. 1ch first. this register is reset at a vdd27-por or xres input. bit bit name default access bit description 7 cvdd1_fast 0 r/w selects a faster regulation mode for cvdd1 suitable for larger load changes. 0: normal mode, cext=10f 1: fast mode, cext=22f required 6:0 vsel_cvdd1<6:0> 000000 r/w the voltage select bits set the dc/dc output voltage level and power the dc/dc converter down. 00h: dc/dc powered down 01h-40h: cvdd1=0.6v+vsel_cvdd1*12.5mv 41h-70h: cvdd1=1.4v+( vsel_cvdd1-40h)*25mv 71h-7fh: cvdd1=2.6v+(vsel_cvdd1-70h)*50mv table 20. cvdd2 register name base default cvdd2 2-wire serial 00h offset: 17h-2 cvdd2 dc/dc buck regulator control register this is an extended register and needs to be enabled by writing 010b to reg. 1ch first. this register is reset at a vdd27-por or xres input. bit bit name default access bit description 7 cvdd2_fast 0 r/w selects a faster regulation mode for cvdd2 suitable for larger load changes. 0: normal mode, cext=10f 1: fast mode, cext=22f required 6:0 vsel_cvdd2<6:0> 000000 r/w the voltage select bits set the dc/dc output voltage level and power the dc/dc converter down. 00h: dc/dc powered down 01h-40h: cvdd1=0.6v+vsel_cvdd1*12.5mv 41h-70h: cvdd1=1.4v+( vsel_cvdd1-40h)*25mv 71h-7fh: cvdd1=2.6v+(vsel_cvdd1-70h)*50mv ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 39 - 70 as3606 as3607 2v2 data sheet - register definition table 21. cvdd3 register name base default cvdd3 2-wire serial 00h offset: 17h-3 cvdd3 dc/dc buck regulator control register this is an extended register and needs to be enabled by writing 011b to reg. 1ch first. this register is reset at a vdd27-por or xres input. bit bit name default access bit description 7 cvdd3_fast 0 r/w selects a faster regulation mode for cvdd3 suitable for larger load changes. 0: normal mode, cext=10uf 1: fast mode, cext=22uf required 6:0 vsel_cvdd3<6:0> 000000 r/w the voltage select bits set the dc/dc output voltage level and power the dc/dc converter down. 00h: dc/dc powered down 01h-40h: cvdd1=0.6v+vsel_cvdd1*12.5mv 41h-70h: cvdd1=1.4v+( vsel_cvdd1-40h)*25mv 71h-7fh: cvdd1=2.6v+(vsel_cvdd1-70h)*50mv table 22. hibernation register name base default hibernation 2-wire serial 00h offset: 17h-4 pmu hibernation control register hibernation starts when writing this register, except hibernation via gpio is selected. this is an extended register and needs to be enabled by writing 100b to reg. 1ch first. this register is reset at a vdd27-por or xres input. this register must not be read back!!! bit bit name default access bit description 7- 0n/a 6 keep_pvdd4 0 w keeps the programmed pvd d4 level during hibernation. 0: power down pvdd4 1: keep pvdd4 5 keep_pvdd3 0 w keeps the programmed pvd d3 level during hibernation. 0: power down pvdd3 1: keep pvdd3 4 keep_pvdd2 0 w keeps the programmed pvd d2 level during hibernation. 0: power down pvdd2 1: keep pvdd2 3 keep_pvdd1 0 w keeps the programmed pvd d1 level during hibernation. 0: power down pvdd1 1: keep pvdd1 2 keep_cvdd3 0 w keeps the programmed cvdd3 level during hibernation. 0: power down cvdd3 1: keep cvdd3 1 keep_cvdd2 0 w keeps the programmed cvdd2 level during hibernation. 0: power down cvdd2 1: keep cvdd2 0 keep_cvdd1 0 w keeps the programmed cvdd1 level during hibernation. 0: power down cvdd1 1: keep cvdd1 ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 40 - 70 as3606 as3607 2v2 data sheet - register definition table 23. dcdc_cntr register name base default dcdc_cntr 2-wire serial 00h offset: 17h-5 dc/dc step down control register this is an extended register and needs to be enabled by writing 101b to reg. 1ch first. this register is reset at a vdd27-por or xres input. bit bit name default access bit description 7 cfm_cvdd23_off 0 r/w disables pulse skip mode for dcdc2 and dcdc3 0: current force mode / pulse skip enabled 1: current force mode / pulse skip disable 6 cfm_cvdd1_off 0 r/w disables pulse skip mode for dcdc1 0: current force mode / pulse skip enabled 1: current force mode / pulse skip disable 5 cvdd23_freq 0 r/w selects the switch ing frequency for dcdc2 and dcdc 3 0: 2mhz 1: 1mhz 4 cvdd1_freq 0 r/w selects the switching frequency for dcdc1 0: 2mhz 1: 1mhz 3:2 dvm_cvdd23<1:0> 00 r/w configures the dynamic voltage management (output voltage slope) for cvdd2 and cvdd3 00: immediate change of the output voltage 01: 32s/step 10: 128s/step 11: 512s/step 1:0 dvm_cvdd1<1:0> 00 r/w configures the dynamic voltage management (output voltage slope) for cvdd1 00: immediate change of the output voltage 01: 32s/step 10: 128s/step 11: 512s/step ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 41 - 70 as3606 as3607 2v2 data sheet - register definition table 24. gpio_cntr register name base default gpio_cntr 2-wire serial 00h offset: 17h-7 gpio control register this is an extended register and needs to be enabled by writing 111b to reg. 1ch first. this register is reset at a vdd27-por or xres input. bit bit name default access bit description 7:6 mux_gpio43<1:0> 00 r/w configures gpio4 and gpio3 00: hiz / hiz (gpios are inputs) 01: xvsup_low / xcharging 10: xpwrup / pwrgood 11: xeoc / xcharger_active 5 drive_gpio2 0 r/w configures gpio2 as input or output 0: open drain (output) 1: hiz (input) 4:3 mux_gpio2<1:0> 00 r/w configures gpio2 output mode 00: low 01: xvsup_low 10: high 11: xcharging 2 drive_gpio1 0 r/w configures gpio1 as input or output 0: hiz (input) 1: open drain (output) 1:0 mux_gpio1<1:0> 00 r/w configures gpio1 output mode 00: xcharging 01: xvsup_low 10: xpwrup 11: pwrgood table 25. pvdd1 register name base default pvdd1 2-wire serial 00h offset: 18h-1 pvdd1 control register this is an extended register and needs to be enabled by writing 001b to reg. 1ch first. this register is reset at a vdd27-por or xres input. bit bit name default access bit description 7 pvdd1_on 0 r/w enables pvdd1 regulator 0: pvdd1 switched off 1: pvdd1 switched on 6 ilim_h_pvdd1 0 r/w selects the hi gher current limit for pvdd1 0: default mode, 150ma 1: 250ma mode 5 lp_pvdd1 0 r/w selects the low power mode for pvdd1 0: pvdd1 is in normal operation 1: pvdd1 supply current is reduced 4:0 vsel_pvdd1<4:0> 00000 r/w sets the ld o output voltage in register cont rol mode (default voltage of the regulator is selected by boot rom 0x00-0x0f: 1.2v+vsel*50mv (1.2v - 1.95v) 0x10-0x1f: 2.0v + (vsel-0x10)*100mv (2.0v-3.5v) ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 42 - 70 as3606 as3607 2v2 data sheet - register definition table 26. pvdd2 register name base default pvdd2 2-wire serial 00h offset: 18h-2 pvdd2 control register this is an extended register and needs to be enabled by writing 010b to reg. 1ch first. this register is reset at a vdd27-por or xres input. bit bit name default access bit description 7 pvdd2_on 0 r/w enables pvdd2 regulator 0: pvdd2 switched off 1: pvdd2 switched on 6 ilim_h_pvdd2 0 r/w selects the hi gher current limit for pvdd2 0: default mode, 150ma 1: 250ma mode 5 lp_pvdd2 0 r/w selects the low power mode for pvdd2 0: pvdd2 is in normal operation 1: pvdd2 supply current is reduced 4:0 vsel_pvdd2<4:0> 00000 r/w sets the ld o output voltage in register cont rol mode (default voltage of the regulator is selected by the boot rom 0x00-0x0f: 1.2v+vsel*50mv (1.2v - 1.95v) 0x10-0x1f: 2.0v + (vsel-0x10)*100mv (2.0v-3.5v) table 27. pvdd3 register name base default pvdd3 2-wire serial 00h offset: 18h-3 pvdd3 control register this is an extended register and needs to be enabled by writing 011b to reg. 1ch first. this register is reset at a vdd27-por or xres input. bit bit name default access bit description 7 pvdd3_on 0 r/w enables pvdd3 regulator 0: pvdd1 switched off 1: pvdd1 switched on 6 ilim_h_pvdd3 0 r/w selects the hi gher current limit for pvdd3 0: default mode, 150ma 1: 250ma mode 5 lp_pvdd3 0 r/w selects the low power mode for pvdd3 0: pvdd3 is in normal operation 1: pvdd3 supply current is reduced 4:0 vsel_pvdd3<4:0> 00000 r/w sets the ld o output voltage in register cont rol mode (default voltage of the regulator is selected by the boot rom 0x00-0x0f: 1.2v+vsel*50mv (1.2v - 1.95v) 0x10-0x1f: 2.0v + (vsel-0x10)*100mv (2.0v-3.5v) ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 43 - 70 as3606 as3607 2v2 data sheet - register definition table 28. pvdd4 register name base default pvdd4 2-wire serial 00h offset: 18h-4 pvdd4 control register this is an extended register and needs to be enabled by writing 100b to reg. 1ch first. this register is reset at a vdd27-por or xres input. bit bit name default access bit description 7 pvdd4_on 0 r/w enables pvdd4 regulator 0: pvdd4 switched off 1: pvdd4 switched on 6 ilim_h_pvdd4 0 r/w selects the hi gher current limit for pvdd4 0: default mode, 150ma 1: 250ma mode 5 lp_pvdd4 0 r/w selects the low power mode for pvdd4 0: pvdd4 is in normal operation 1: pvdd4 supply current is reduced 4:0 vsel_pvdd4<4:0> 00000 r/w sets the ld o output voltage in register cont rol mode (default voltage of the regulator is selected by the boot rom 0x00-0x0f: 1.2v+vsel*50mv (1.2v - 1.95v) 0x10-0x1f: 2.0v + (vsel-0x10)*100mv (2.0v-3.5v) table 29. vdd27 register name base default vdd27 2-wire serial 00h offset: 18h-5 vdd27 control register this is an extended register and needs to be enabled by writing 101b to reg. 1ch first. this register is reset at a vdd27-por or xres input. bit bit name default access bit description 7 prg_vdd27 0 n/a selects the output voltage control mode for vdd27 0:vdd27 is in default mode 1: vdd27 is register controlled (reg. 18-5h) 6 ilim_h_vdd27 0 r/w selects the higher current limit for vdd27 0: default mode, 100ma 1: 200ma mode 5 lp_vdd27 0 r/w selects the low power mode for vdd27 0: vdd27 is in normal operation 1: vdd27 supply current is reduced 5- 0n/a 3:0 vsel_vdd27<3:0> 0000 r/w sets the ld o output voltage in register cont rol mode (default voltage of the regulator is 2.7v) 0x0-0x2: 2.3v 0x3-0xf: 2.0v + vsel*100mv (2.3v-3.5v) ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 44 - 70 as3606 as3607 2v2 data sheet - register definition table 30. chg_cntr register name base default chg_cntr 2-wire serial c9h offset: 19h-0 charger control register this is an extended register but does not need to be enabled as reg. 1ch is 000b per default. this register is reset at a vdd27-por or xres input. bit bit name default access bit description 7 bat_det_off 1 r/w disables the battery detection 0: battery detection switched on 1: battery detection switched off 6 auto_resume 1 r/w defines the behavior after end of charge (eoc) 0: auto resume is disabled 1: auto resume enabled, charger will start charging when vbatsw drops below the resume level 5 bat_charge_on 0 r/w enables the battery charging 0: vsup is supplied via usb pre-regulator, but the battery switch is open 1: normal battery charging operation from usb pre-regulator 4:1 usb_currlim <3:0> 1000 r/w sets the usb pre-regulator current limit 0x0: 94ma (usb low current) 0x1: 141ma 0x2: 189ma 0x3: 237ma 0x4: 285ma 0x5: 332ma 0x6: 380ma 0x7: 428ma 0x8: 470ma (usb high current) 0x9: 517ma 0xa: 599ma 0xb: 760ma 0xc: 882ma 0xd: 1060ma 0xe, 0xf: do not use 0 usb_prereg_on 1 r/w enables the usb pre-regulator and current limiter 0: usb pre-regulator is switched off 1: usb pre-regulator supplies vsup from vusb input ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 45 - 70 as3606 as3607 2v2 data sheet - register definition table 31. chg_vcntr register name base default chg_vcntr 2-wire serial 36h offset: 19h-1 charger voltage control register this is an extended register and needs to be enabled by writing 001b to reg. 1ch first. this register is reset at a vdd27-por or xres input. bit bit name default access bit description 7:5 chg_v_resume <2:0> 001 r/w sets the charger auto resume voltage threshold 000: 3.85v 001: 3.90v 010: 3.95v 011: 4.00v 100: 4.05v 101: 4.10v 110: 4.15v 111: 4.20v 4:3 vsup_min<1:0> 10 r/w defines the minimum vsup voltage during trickle or constant current charging. the charging current will be reduced if vsup would drop below this threshold. 00: 3.9v 01: 3.6v 10: 4.2v 11: 4.5v 2:0 chg_v_eoc <2:0> 110 r/w sets the charger end of charge voltage threshold 000: 3.90v 001: 3.95v 010: 4.00v 011: 4.05v 100: 4.10v 101: 4.15v 110: 4.20v 111: 4.25v ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 46 - 70 as3606 as3607 2v2 data sheet - register definition table 32. chg_icntr register name base default chg_vcntr 2-wire serial 21h offset: 19h-2 charger current control register this is an extended register and needs to be enabled by writing 010b to reg. 1ch first. this register is reset at a vdd27-por or xres input. bit bit name default access bit description 7:4 chg_i_constant <3:0> 0010 r/w sets the current during constant current charging 0x0: 94ma 0x1: 141ma 0x2: 189ma 0x3: 237ma 0x4: 285ma 0x5: 332ma 0x6: 380ma 0x7: 428ma 0x8: 470ma 0x9: 517ma 0xa: 599ma 0xb: 760ma 0xc: 882ma 0xd: 1060ma 0xe, 0xf: do not use 3:0 chg_i_trickle <3:0> 0001 r/w sets the current during constant current charging 0x0: 24ma 0x1: 35ma 0x2: 47ma 0x3: 59ma 0x4: 71ma 0x5: 83ma 0x6: 95ma 0x7: 107ma 0x8: 118ma 0x9: 129ma 0xa: 150ma 0xb: 190ma 0xc: 221ma 0xd: 265ma 0xe, 0xf: do not use ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 47 - 70 as3606 as3607 2v2 data sheet - register definition table 33. chg_config register name base default chg_config 2-wire serial 15h offset: 19h-3 charger configuration register this is an extended register and needs to be enabled by writing 011b to reg. 1ch first. this register is reset at a vdd27-por or xres input. bit bit name default access bit description 7:5 - 000 n/a 4:3 chg_i_eoc<1:0> 10 r/w configures the end of charge current threshold. charging will be stopped if the current drops below the threshold. 00: 8% of constant current setting 01: 15% 10: 10% 11: 20% 2:0 vsup_eoc <2:0> 101 r/w defines vsup voltage after eoc and isolated battery. 000: 4.3v 001: 4.4v 010: 4.5v 011: 4.6v 100: 4.7v 101: 4.8v 110: 4.9v 111: 5.0v table 34. chg_ntc register name base default chg_ntc 2-wire serial 01h offset: 19h-4 charger ntc control register this is an extended register and needs to be enabled by writing 100b to reg. 1ch first. this register is reset at a vdd27-por or xres input. bit bit name default access bit description 7:3 - 0000 0 n/a 2 ntc_mode 0 r/w defines the temperature level for the battery temperature supervisor to stop charging. (for beta of ntc = 4250) 0: 55oc 1: 45oc 1 ntc_10k 0 r/w defines the type of ntc used for battery temperature supervisor. 0: 100k 1: 10k 0 ntc_on 1 r/w enables the battery temperature supervisor via ntc resistor. 0: ntc battery temp supervision disabled 1: ntc battery temp supervision enabled ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 48 - 70 as3606 as3607 2v2 data sheet - register definition table 35. chg_time register name base default chg_time 2-wire serial 07h offset: 19h-5 charger time control register this is an extended register and needs to be enabled by writing 101b to reg. 1ch first. this register is reset at a vdd27-por or xres input. bit bit name default access bit description 7:5 - 0000 0 n/a 4 tmax_timer 0 r returns the time-out supervision status 0: no time-out reached 1: charger time-out reached, charging stopped w resets the charger time supervision 0: - 1: resets time-out counter 3:0 chg_timeout <3:0> 0111 r/w sets the current during constant current charging 0x0: charger timer disabled 0x1: 0.5h 0x2: 1h 0x3: 1.5h 0x4: 2h 0x5: 2.5h 0x6: 3h 0x7: 3.5h 0x8: 4h 0x9: 4.5h 0xa: 5h 0xb: 5.5h 0xc: 6h 0xd: 6.5h 0xe: 7h 0xf: 7.5h table 36. chg_stat1 register name base default chg_stat1 2-wire serial xxh offset: 19h-6 charger status register 1 this is an extended register and needs to be enabled by writing 110b to reg. 1ch first. this register is reset at a vdd27-por or xres input. bit bit name default access bit description 7 no_bat x r status if a battery is detected to the system, by measuring the ntc value on battemp pin. 0: battery detected 1: no battery detected 6 battemp_high x r only valid if a charger is deducted. 0: battery temperature o.k. 1: battery temperature higher 55oc/45oc (seed ntc_mode ) 5 eoc x r 0: end of charge not reached. bit is cleared automatically if usb_prereg_on or bat_charge_on is cleared or resume state is entered 1: end of charge reached ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 49 - 70 as3606 as3607 2v2 data sheet - register definition 4 cv x r 1: if charger is in constant voltage (top-off charge) mode 3 trickle x r 1: if charger is in trickle charging mode 2 resume x r 1: if vbatsw dropped below resume threshold 1 cc x r 1: if charger is in constant current charging mode 0 chg_det x r 1: if a charger adapter is detected on vusb pin table 37. chg_stat2 register name base default chg_stat2 2-wire serial xxh offset: 19h-7 charger status register 2 this is an extended register and needs to be enabled by writing 111b to reg. 1ch first. this register is reset at a vdd27-por or xres input. bit bit name default access bit description 7:3 - xxxx xx n/a 1:0 batsw_mode <1:0> x r shows the battery switch operation mode 00: battery switch open, no ideal diode operation (just for charger start-up) 01: battery switch open, ideal diode operation (charger connected but eoc reached) 10: battery switch acting as a voltage limited current source (charging) 11: battery switch closed (charger disconnected) table 36. chg_stat1 register name base default chg_stat1 2-wire serial xxh offset: 19h-6 charger status register 1 this is an extended register and needs to be enabled by writing 110b to reg. 1ch first. this register is reset at a vdd27-por or xres input. bit bit name default access bit description ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 50 - 70 as3606 as3607 2v2 data sheet - register definition table 38. out_cntr register name base default out_cntr 2-wire serial 00h offset: 1ah-1 dcdc mode and xirq output control register this is an extended register and needs to be enabled by writing 001b to reg. 1ch first. this register is reset at a vdd27-por or xres input. bit bit name default access bit description 7 dcdc23_1.4a 0 r/w combines dcdc2 and dcdc3 to one regulator for 1.4a output currents 0: dcdc2 and dcdc3 working independent 1: dcdc2 & dcdc3 combined for 1.4a (dcdc3 registers have no effect) 6 gpio_hbn_on 0 r/w 0: hibernation enable via gpios disabled 1: hibernation enalbe via gpios enabled gpio selected via gpio_dimm_hbn_sel <1:0> 5:4 hbn_delay<1:0> 00 r/w sets the delay time for going into hibernation after writing to register 17-4h 00: 0ms 01: 8ms 10: 16ms 11: 32ms 3:2 drive_xirq<1:0> 00 r/w sets the xirq output pin to open-drain, push-pull or tri-state and sets various driving strengths 00: 6ma open-drain output 01: 6ma push-pull output 10: 1ma push-pull output 11: hiz, tri-state 1:0 mux_xirq<1:0> 00 r/w multiplexes various digital signals to the xirq output pin 00: xirq, active low interrupt request signal 01: clkint1, internal clock signal, see clk_cntr register 10: clkint2, internal clock signal, see clk_cntr register 11: irq, active low reset signal table 39. clk_cntr register name base default clk_cntr 2-wire serial 00h offset: 1ah-2 clock control register this is an extended register and needs to be enabled by writing 010b to reg. 1ch first. this register is reset at a vdd27-por or xres input. bit bit name default access bit description 7:6 clkint2<1:0> 00 r/w selects the clkint2 input source. note, this is an internal clock, which can be multiplexed to the xres output. 00: low, drives the signal to logic ?0? 01: clk1hz charger 10: do not use 11: high, drives the signal to logic ?1? 5:4 clkint1<1:0> 00 r/w selects the clkint1 frequency. note, this is an internal clock, which can be multiplexed to xirq output. 00: 2mhz 01: 1mhz 10: 1khz 11: 125hz ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 51 - 70 as3606 as3607 2v2 data sheet - register definition 3:2 gpio_dimm_hbn_sel <1:0> 00 r/w selects input for external dimming or hibernation control 00: disable dimming or hibernation via gpio 01: gpio1 10: gpio2 11: gpio3 1:0 - 00 n/a table 40. boost_cntr1 register name base default boost_cntr1 2-wire serial 00h offset: 1bh-1 dcdc step-up control register 1 this is an extended register and needs to be enabled by writing 001b to reg. 1ch first. this register is reset at a vdd27-por or xres input. bit bit name default access bit description 7 su_on 0 r/w enables the dcdc step-up regulator 0: su switched off 1: su switched on (will be reset if vfb exceeds the maximum and the current drops to zero) 6- 0n/a 5 su_slowdim 0 r/w selects the dcdc step-up regulator external dimming mode 0: for dimming frequencies <1khz 1: for dimming frequencies >1khz 4:3 su_extdim<1:0> 00 r/w selects the dcdc step-up external pwm dimming input 00: no ext. dimming 01: curr1 controlled 10: curr2 controlled 11: gpio1/2/3 controlled (selected via gpio_dimm_hbn_sel <1:0> ) 2 su_ovp_off 0 r/w disables the dcdc step-up over-voltage protection 0: su ovp switched on 1: su ovp switched off 1 su_curr_fb 0 r/w selects the dcdc step-up feedback mode 0: voltage fb via pin fbsu 1: current feedback via curr1 or curr2 (automatic select) 0 su_fastskip 0 r/w defines the dcdc step-up regulator output voltage at low loads, when pulse skipping is active 0: accurate output voltage, more ripple 1: elevated output voltage, less ripple table 39. clk_cntr register name base default clk_cntr 2-wire serial 00h offset: 1ah-2 clock control register this is an extended register and needs to be enabled by writing 010b to reg. 1ch first. this register is reset at a vdd27-por or xres input. bit bit name default access bit description ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 52 - 70 as3606 as3607 2v2 data sheet - register definition table 41. boost_cntr2 register name base default boost_cntr2 2-wire serial 00h offset: 1bh-2 dcdc step-up control register 2 this is an extended register and needs to be enabled by writing 010b to reg. 1ch first. this register is reset at a vdd27-por or xres input. bit bit name default access bit description 7:3 su_ifb<4:0> 0 0000 r/w defines the tuning current at pin fbsu. 0x00: 0a 0x01: 1a 0x02: 2a ... 0x1f: 31a 2 su_currlim 0 r/w selects the dcdc step -up converter coil current limit 0: normal current limit 1: current limit increased by about 50% 1 su_gain 0 r/w dcdc step-up converter feedback gain is selected automatically depending on current or voltage feedback mode. setting this bit to ?1? will choose the alternative feedback gain setting. 0 su_freq 00 r/w defines the dcdc step-up switching frequency 0: 1mhz 1: 500khz table 42. curr1 register name base default curr1 2-wire serial 00h offset: 1bh-3 current sink 1 register this is an extended register and needs to be enabled by writing 011b to reg. 1ch first. this register is reset at a vdd27-por or xres input. bit bit name default access bit description 7:0 icurr1<7:0> 0x00 r/w sets the current for current sink 1 in 255 steps with 140.626a stepsize 0x00: current sink 1 switched off 0x01: 0.15 ma 0x02: 0.30 ma 0x03: 0.45 ma .. 0xfe: 38,10 ma 0xff: 38.25 ma ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 53 - 70 as3606 as3607 2v2 data sheet - register definition table 43. curr2 register name base default curr2 2-wire serial 00h offset: 1bh-4 current sink 2 register this is an extended register and needs to be enabled by writing 100b to reg. 1ch first. this register is reset at a vdd27-por or xres input. bit bit name default access bit description 7:0 icurr2<7:0> 0x00 r/w sets the current for current sink 2 in 255 steps with 140.626a stepsize 0x00: current sink 2 switched off 0x01: 0.141 ma 0x02: 0.281 ma 0x03: 0.422 ma .. 0xfe: 35,72 ma 0xff: 35.86 ma table 44. pmu_enable register name base default pmu_enable 2-wire serial 00h offset: 1ch pmu_enable register selects the extended register on address 17h to 1bh and enables writing to these pmu register. it also sets the adc10 multiplexer to measure various regulator voltages this register is reset at a vdd27-por or xres input. bit bit name default access bit description 7:4 dc_test_mux <3:0> 0000 r/w allows multiplexing internal and external supply voltages to one dc test node which can be further multiplexed to the adc10. the accuracy is 5mv/ lsb (see reg. 2eh) 0x0: open 0x1: pvdd1 0x2: pvdd2 0x3: pvdd3 0x4: pvdd4 0x5: vdd27 0x6: cvdd1 0x7: cvdd2 0x8: cvdd3 0x9-0xf: n/a 3 pmu_gate 0 r/w enables all settings made in registers 17h to 1bh at once. if this bit is set, changes are activated as soon as they are written to the related register. 0: no change 1: change at once 2:0 pmu_enable <2:0> 000 r/w selects extended registers 17h to 1bh for the next read or write. this register has to be set before every read or write even if the selection is not changing. 0: 19h-0 selected 1: 17h-1 to 1bh-1 selected 2: 17h-2 to 1bh-2 selected ... 7: 17h-7 to 1bh-7 selected ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 54 - 70 as3606 as3607 2v2 data sheet - register definition table 45. system register name base default system 2-wire serial 51h offset: 20h system register this register is reset at a vdd27-por or xres input. bit bit name default access bit description 7:4 design_version<3:0> 0101 r number to identify the design version 0101: for chip version 2v2 3- 0n/a 2 jtemp_sup_off 0 r/w junction temperature supervision (level can be set in register 21h) 0: temperature supervision enabled 1: temperature supervision disabled 1 i2c_wd_on 0 r/w 2-wire serial interface watchdog to reset the watchdog counter a 2-wire serial read operation has to be performed at least every 500ms. if the watchdog counter is not reset, the pmu will be powered down. 0: watchdog is disabled 1: watchdog is enabled 0 pwr_hold 1 r/w 0: power up hold is cleared and pmu will power down 1: is automatically set to on after power on table 46. supervisor1 register name base default supervisor1 2-wire serial 00h offset: 21h supervisor register 1 this register is reset at a vdd27-por or xres input. bit bit name default access bit description 7:6 pwrup_sd_xres <1:0> 00 r/w applying a high signal on pwrup pin for about 8s will 00: perform a reset cycle 01: have no effect 10: initiate a shut-down 11: initiate a shut-down 5 sd_xres_time 0 r/w halfs the time from pulling pwrup high to xres or sd 0: 8s 1: 4s 4:0 jtemp_sup<4:0> 0 r/w sets the threshold for junction temperature emergency shutdown and junction temperature interrupt invoke shutdown at: jtemp_sd=140-jtemp_sup*5oc invoke interrupt at: jtemp_irq=120-jtemp_sup*5oc jt_sup 00000 00001 . . 11110 11111 irq 120c 115c . . -30c -35c shutdown 140c 135c . . -10c -15c ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 55 - 70 as3606 as3607 2v2 data sheet - register definition table 47. supervisor2 register name base default supervisor2 2-wire serial 00h offset: 22h supervisor register 2 this register is reset at a vdd27-por or xres input. bit bit name default access bit description 7:6 - 00 n/a 5 vdd27low_sd_off 0 r/w 0: vdd27low (vdd27 - 10%) shut down enabled 1: vdd27low shut down disabled 4 vsuplow_sd_on 0 r/w 0: vsuplow shut down enabled 1: vsuplow shut down disabled 3:1 vsuplow_sup<2:0> 000 r/w sets the threshold for vsup supervisor 000: 2.7v 001: 2.9v 010: 3.1v 011: 3.2v 100: 3.3v 101: 3.4v 110: 3.5v 111: 3.6v 0 vsuplow_sup_off 0 r/w 0: vsuplow supervision enabled 1: vsuplow supervision disabled ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 56 - 70 as3606 as3607 2v2 data sheet - register definition table 48. first interrupt register name base default irqenrd_0 2-wire serial 00h offset: 23h first interrupt register please be aware that writing to this register will enable/disable the corresponding interrupts, while reading gets the actual interrupt status and will clear the register at the same time. it is not possible to read back the interrupt enable/disable settings. this register is reset at a vdd27-por or xres input. bit bit name default access bit description 7 cvdd1_sd 0 w invokes shut-down of the pmu when a ?10% under-voltage spike at cvdd1 occurs 0: disable 1: enable cvdd1_under x r this bit is set when a ?5% under-voltage at cvdd1 occurs 6 cvdd1_irq 0 w enables interrupt for over-voltage/under-voltage supervision of cvdd1 0: disable 1: enable cvdd1_over x r this bit is set when a +8% over-voltage at cvdd1 occurs 5 cvdd2_sd 0 w invokes shut-down of the pmu when a ?10% under-voltage spike at cvdd2 occurs 0: disable 1: enable cvdd2_under x r this bit is set when a ?5% under-voltage at cvdd2 occurs 4 cvdd2_irq 0 w enables interrupt for over-voltage/under-voltage supervision of cvdd2 0: disable 1: enable cvdd2_over x r this bit is set when a +8% over-voltage at cvdd2 occurs 3 cvdd3_sd 0 w invokes shut-down of the pmu when a ?10% under-voltage spike at cvdd3 occurs 0: disable 1: enable cvdd3_under x r this bit is set when a ?5% under-voltage at cvdd3 occurs 2 cvdd3_irq 0 w enables interrupt for over-voltage/under-voltage supervision of cvdd3 0: disable 1: enable cvdd3_over x r this bit is set when a +8% over-voltage at cvdd3 occurs 1:0 - 00 n/a ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 57 - 70 as3606 as3607 2v2 data sheet - register definition table 49. second interrupt register name base default irqenrd_1 2-wire serial 00h offset: 24h second interrupt register please be aware that writing to this register will enable/disable the corresponding interrupts, while reading gets the actual interrupt status and will clear the register at the same time. it is not possible to read back the interrupt enable/disable settings. this register is reset at a vdd27-por or xres input. bit bit name default access bit description 7 pwrup_irq 0 w enables interrupt which is invoked whenever a high signal at the pwrup input pin occurs 0: disable 1: enable x r this bit is set whenever a high level of min. vsup/3 at the pwrup input pin occurs (pwrup pin is commonly connected to the power-up button) 6 gpio1_irq 0 w enables interrupt which is invoked whenever a high signal at the gpio1 input pin occurs 0: disable 1: enable x r this bit is set whenever a high level of min. tbd at the gpio1 input pin occurs 5 gpio2_irq 0 w enables interrupt which is invoked whenever a high signal at the gpio2 input pin occurs 0: disable 1: enable x r this bit is set whenever a high level of min. tbd at the gpio2 input pin occurs 4 gpio3_irq 0 w enables interrupt which is invoked whenever a high signal at the gpio3 input pin occurs 0: disable 1: enable x r this bit is set whenever a high level of min. tbd at the gpio3 input pin occurs 3 gpio4_irq 0 w enables interrupt which is invoked whenever a high signal at the gpio4 input pin occurs 0: disable 1: enable x r this bit is set whenever a high level of min. tbd at the gpio4 input pin occurs 2:0 - 000 n/a ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 58 - 70 as3606 as3607 2v2 data sheet - register definition table 50. third interrupt register name base default irqenrd_2 2-wire serial 00h offset: 25h third interrupt register please be aware that writing to this register will enable/disable the corresponding interrupts, while reading gets the actual interrupt status and will clear the register at the same time. it is not possible to read back the interrupt enable/disable settings. this register is reset at a vdd27-por or xres input. bit bit name default access bit description 7 chg_temp_irq (status change) 0 w battery over-temperature interrupt setting 0: disable 1: enable interrupt if chg_temp status bit changes chg_temp x r battery over-temperature status reading 0: battery temperature below off-threshold 1: battery temperature was too high and the charger was turned off. the charger will be turned on again, when the temperature gets below the on- threshold 6 chg_eoc_irq (status change) 0 w charger end of charge interrupt setting. 0: disable 1: enable interrupt if chg_eoc status bit changes chg_eoc x r charger end of charge status reading 0: battery charging in progress 1: charging is complete, charging current is below selected level of nominal current, charger was turned off. 5 chg_nobat_irq (status change) 0 w charger no battery interrupt setting 0: disable 1: enable interrupt if chg_nobat status bit changes chg_nobat x r charger no battery status reading 0: battery connected 1: no battery detected at vbatsw pin 4 chg_det_irq (status change) 0 w charger detect interrupt setting. 0: disable 1: enable interrupt if chg_det status bit changes chg_det x r charger detect status reading 0:charger disconnected 1: charger connected 3- 0n/a 2 icurr_lv_irq (level) 0 w current sink undervoltage interrupt setting. 0: disable 1: enable interrupt if the outputvoltage of one of the current sinks gets below the target regulation voltage x r current sink undervoltage status reading 0: normal voltage on icurr1 and icurr2 1: voltage at icurr1 or icurr2 dropped below target voltage ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 59 - 70 as3606 as3607 2v2 data sheet - register definition 1 vsup_low_irq (level) 0 w vsup under-voltage supervisor interrupt setting 0: disable 1: enable x r vsup supervisor interrupt reading 0: vsup is above brown out level 1: vsup has reached brown out level the threshold can be set with vsuplow_sup<2:0> in supervisor2 register (22h). if the shutdown is enabled the interrupt will not occur. 0 vdd27_low_irq (level) 0 w vdd27 undervoltage supervisor interrupt setting 0: disable 1: enable x r vdd27 supervisor interrupt reading 0: vdd27 is above threshold out level 1: vdd27 has reached threshold level (vdd27-10%). if the shutdown is enabled the interrupt will not occur. table 50. third interrupt register name base default irqenrd_2 2-wire serial 00h offset: 25h third interrupt register please be aware that writing to this register will enable/disable the corresponding interrupts, while reading gets the actual interrupt status and will clear the register at the same time. it is not possible to read back the interrupt enable/disable settings. this register is reset at a vdd27-por or xres input. bit bit name default access bit description ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 60 - 70 as3606 as3607 2v2 data sheet - register definition table 51. fourth interrupt register name base default irqenrd_3 2-wire serial 00h offset: 26h fourth interrupt register please be aware that writing to this register will enable/disable the corresponding interrupts, while reading gets the actual interrupt status and will clear the register at the same time. it is not possible to read back the interrupt enable/disable settings. this register is reset at a vdd27-por or xres input. bit bit name default access bit description 7:6 - 00 r/w 5 t_deb<1:0> 0 r/w sets the de-bounce time all interrupt inputs: 0: 3ms 1: off 4:3 - 00 r/w 2jtemp_high (level) 0 w supervisor junction over-temperature interrupt setting 0: disable 1: enable x r supervisor junction over-temperature interrupt reading 0: chip temperature below threshold 1: chip temperature has reached the threshold the threshold can be set in the supervisor register (21h) 1- 0r/w 0adc_eoc (edge) 0 w adc end of conversion interrupt setting 0: disable 1: enable x r adc end of conversion interrupt reading 0: adc conversion not finished 1: adc conversion finished. read out adc10_0 and adc10_1 register to get the result (2eh & 2fh) ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 61 - 70 as3606 as3607 2v2 data sheet - register definition table 52. adc10_0 register name base default adc10_0 2-wire serial 0000 00xxb offset: 2eh first 10-bit adc register writing to this register will start the measurement of the selected source. this register is reset at a vdd27-por, exception are bit 0 and 1 bit bit name default access bit description 7:4 adc10_mux<3:0> 0000 r/w selects adc input source 0000: vsup 0001: gpio3 0010: gpio4 0011: vbatsw 0100: vusb 0101: defined by dc_test in register 0x1c 0110: battemp 0111: gpio1 1000: gpio2 1001:pwrup 1010: reserved 1011: reserved 1100: vbe_1ua 1101: vbe_2ua 1110: reserved 1101: reserved 3:2 - 00 n/a 1:0 adc10<9:8> xx r adc result bit 9 to 8 table 53. adc10_1 register name base default adc10_1 2-wire serial xxh offset: 2fh second 10-bit adc register this register is reset at a vdd27-por. bit bit name default access bit description 7:0 adc10<7:0> 00h r adc results bits 7 to 0 ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 62 - 70 as3606 as3607 2v2 data sheet - application information 11 application information 11.1 pad cells figure 21. pad cells equivalant circuit ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 63 - 70 as3606 as3607 2v2 data sheet - application information 11.2 application schematics figure 22. typical as3606 application schematic 1 1 2 2 3 3 4 4 d d c c b b a a title size date project title revision sheet of originator dgm as3606 eval board v1.1 17.02.2010 4 3 a4 c4 2.2uf c3 10uf c6 2.2uf c5 2.2uf c18 15nf c13 2.2uf c11 4.7uf c10 2.2uf c12 2.2uf c17 1.5nf gnd gnd gnd l1 2.2uh l2 2.2uh l3 2.2uh c2 10uf c1 10uf gnd gnd gnd c15 2.2uf gnd gnd r5 910k r7 100k q1 fdc602p c7 10uf gnd bu12 vbat+ bu13 vbat- gnd c8 10uf l4 10uh d1 vsup c9 2.2uf d3 d5 d8 d10 gnd gnd c16 2.2uf gnd vsup vsup d11 d14 pwrup cscl csda xres xriq j11 on r6 100r d6 on led gnd battemp cvdd1 cvdd2 cvdd3 pvdd1 pvdd2 pvdd3 vdd27 gpio1 gpio2 gnd vdcdc_su extbatsw lx2 lx3 r13 0r lx2 lx3 r14 0r gnd c19 10uf gnd combine dcdc sd 2 and 3 to 1.2a mode remove l3 in this application cvdd3 cvdd2 vsup vbat fb_su gnd gnd gnd q2 ndt014l r17 0r q2 optional: for 50v only c20 10uf gnd 1 1 2 2 3 3 4 4 5 5 6 6 j3 usb - box interface usb - box interface / i2c interface gnd csda cscl xriq r2 10k r3 10k r1 10k dvdd xres r15 10k dvdd s2 on xres reset gnd s1 on power on pwrup vsup bus_pwr 1 d- 2 d+ 3 bus_gnd 4 shield 5 u2 usb mini gnd d16 vsup1 11 lxc1 12 cvdd1 13 vsup2 31 lxc2 30 cvdd2 29 vsup3 26 lxc3 27 cvdd3 28 pvdd1 9 pvdd2 8 vsup4 10 pvdd3 7 vdd 27 5 vsup5 6 vbatsw 32 extbatsw 3 vsupsw 1 vusb 2 battemp 4 cscl 20 csda 21 gpio1 19 gpio2 18 xres 24 xirq 23 pwrup 22 lxsu 16 fbsu 17 curr1 15 curr2 14 prg ldos dcdc sd 1-3 interface / gpios / vss dcdc su 30v charger as3606 system pmu with hv bl driver vss 33 dvdd 25 u1 as3606_qfn32 ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 64 - 70 as3606 as3607 2v2 data sheet - application information figure 23. typical as3607 application schematic 1 1 2 2 3 3 4 4 d d c c b b a a title size date project title revision sheet of originator dgm as3607 application circuit * 17.02.2010 4 3 a4 c4 2.2uf c3 10uf c6 2.2uf c5 2.2uf c18 15nf c11 2.2uf c10 4.7uf c12 2.2uf c17 1.5nf gnd gnd gnd l1 2.2uh l2 2.2uh l3 2.2uh c2 10uf c1 10uf gnd gnd gnd c14 2.2uf c15 2.2uf gnd gnd r5 910k r7 100k q1 fdc602p c7 10uf gnd bu12 vbat+ bu13 vbat- gnd c8 1uf l4 10uh d1 vsup c9 2.2uf d3 d5 d8 d10 gnd gnd c16 2.2uf gnd vsup vsup d11 d14 battemp cvdd1 cvdd2 cvdd3 pvdd1 pvdd2 pvdd3 vdd27 curr1 gpio1 gpio2 gnd vdcdc_su extbatsw lx2 lx3 r13 0r lx2 lx3 r14 0r gnd c19 10uf gnd combine dcdc sd 2 and 3 to 1.2a mode remove l3 in this application cvdd3 cvdd2 vsup vbat fb_su gnd gnd gnd q2 ndt014l r17 0r q2 optional: for 50v only c20 10uf gnd pwrup cscl csda xres xriq r6 100r d6 on led gnd pvdd4 c24 2.2uf gnd gpio3 gpio4 dvdd bus_pwr 1 d- 2 d+ 3 bus_gnd 4 shield 5 u2 usb mini gnd d16 1 1 2 2 3 3 4 4 5 5 6 6 j3 cpu - if interface gnd csda cscl xriq r2 10k r3 10k r1 10k dvdd xres r15 10k q1: optional s1 on power on s2 on xres reset gnd pwrup vsup vsup1 13 lxc1 14 cvdd1 15 vsup2 35 lxc2 34 cvdd2 33 vsup3 30 lxc3 31 cvdd3 32 pvdd1 11 pvdd2 10 vsup4 12 pvdd4 7 vdd 27 6 vsup5 8 vbatsw 36 extbatsw 5 vsupsw 2 vusb 3 battemp 4 cscl 24 csda 25 gpio1 22 gpio2 21 xres 28 xirq 27 pwrup 26 lxsu 18 fbsu 19 curr1 17 curr2 16 prg ldos dcdc sd 1-3 interface / gpios / vss dcdc su 30v charger as3607 system pmu with hv bl driver vss 37 dvdd 29 vbatsw 1 pvdd3 9 gpio4 20 gpio3 23 * as3607_qfn36 ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 65 - 70 as3606 as3607 2v2 data sheet - pack age drawings and markings 12 package drawin gs and markings figure 24. as3606 qfn32, 0.5mm pitch ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 66 - 70 as3606 as3607 2v2 data sheet - pack age drawings and markings figure 25. as3607 qfn36, 0.5mm pitch ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 67 - 70 as3606 as3607 2v2 data sheet - pack age drawings and markings figure 26. qfn marking table 54. package code yywwzzz yy ww x zz year working week assembly / packaging plant identifier free choice table 55. start-up revision code xx sequence ff engineering samples, no sequence programmed or sequence programmed on request 00 default sequence (no sequence programmed) xx customer specified sequence programmed during production test ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 68 - 70 as3606 as3607 2v2 data sheet - revision history revision history note: typos may not be explicitly mentioned under revision history. revision date owner description 1.00 7.2010 pkm first official release 1.01 9.2010 pkm corrected gpio2 bit description & gpio hibernation description updated package drawings 1.02 11.2010 pkm corrected charger block diagram, updated package drawings 1.03 3.2011 pkm added ntc supply description, added usb rising edge specification ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 69 - 70 as3606 as3607 2v2 data sheet - ordering information 13 ordering information the devices are available as the standard products shown in table 56 . note: all products are rohs compliant and austriamicrosystems green. buy our products or get free samples online at icdirect: http://www.austriamicr osystems.com/icdirect technical support is found at http://www.austriamicrosystems.com/technical-support for further information and requests, please contact us mailto:sales@austriamicrosystems.com or find your local distributor at http://www.austriamicros ystems.com/distributor table 56. ordering information ordering code marking sequence description delivery form package as3606-bqfp-ff r2v2-ff sequence programmable on request system pmu with hv backlight tape & reel dry pack qfn32 5x5 0.5mm pitch AS3606-BQFP-00 r2v2-00 default sequence system pmu with hv backlight tape & reel dry pack qfn32 5x5 0.5mm pitch as3606-bqfp-xx r2v2-xx customer specified system pmu with hv backlight tape & reel dry pack qfn32 5x5 0.5mm pitch as3607-bqfp-ff r2v2-ff sequence programmable on request system pmu with hv backlight tape & reel dry pack qfn36 6x6 0.5mm pitch as3607-bqfp-00 r2v2-00 default sequence system pmu with hv backlight tape & reel dry pack qfn36 6x6 0.5mm pitch as3607-bqfp-xx r2v2-xx customer specified system pmu with hv backlight tape & reel dry pack qfn36 6x6 0.5mm pitch ams ag technical content still valid
www.austriamicrosystems.com revision 1.03 70 - 70 as3606 as3607 2v2 data sheet - copyright copyright copyright ? 1997-2010, austriamicrosystems ag, tobelbaderstrasse 30, 8141 unterpremstaetten, austria-europe. trademarks registe red ?. all rights reserved. the material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by austriamicrosystems ag are covered by the warranty and patent indemnification provisions appearing in its term of sale. austriamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding the information set forth he rein or regarding the freedom of the described devices from patent infringement. au striamicrosystems ag reserves the right to change specificatio ns and prices at any time and without notice. therefore, prior to designing this product into a system, it is necessary to check with austriamic rosystems ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temper ature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems ag for each application. for shipments of les s than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. the information furnished here by austriamicrosystems ag is believed to be correct and accurate. however, austriamicrosystems ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. no obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or other services. contact information headquarters austriamicrosystems ag tobelbaderstrasse 30 a-8141 unterpremstaetten, austria tel: +43 (0) 3136 500 0 fax: +43 (0) 3136 525 01 for sales offices, distributors and representatives, please visit: http://www.austriamicrosystems.com/contact ams ag technical content still valid

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